STW5095 Datasheet, PDF (66/69 Pages) STMicroelectronics – Low Power Asynchronous Stereo Audio Codec with Integrated Power Amplifiers

17 Application Schematics
17 Application Schematics
STw5095
Figure 31. STw5095 application schematics
2.7kΩ
750Ω
100nF
10µF
Electret
100nF
750Ω
2.7kΩ
2.7kΩ
750Ω
100nF
10µF
2.7kΩ
Electret
750Ω
100nF
200nF
MBIAS
MIC1LP
MIC1LN
MIC1RP
MIC1RN
CAPMIC
Line IN ^L
R
Melody IN
Voice IN
100nF
100nF
0.47µF
0.47µF
0.47µF
L
FM IN
R
16/ 32Ω Typ
40mW Max.
Differential
Connector
0.47µF
0.47µF
10µF
LINEINL
LINEINR
AUX1L
AUX1R
AUX2LP
AUX2RP
AUX2LN
AUX2RN
AUX3L
AUX3R
CAPLINEIN
STw5095
Standard HP
Connection
As Close as
possible to
the pins
SENSE
10µF
HPR
VCMHP
VCMHPS
HPL
CAPLS
8Ω typ
500mW Max.
As Close as
possible to
the pins
SENSE
LSP
LSPS
SENSE
LSNS
LSN
L
Line OUT
R
Leave the negative pins
unconnected when used in
Single-Ended Configuration
OLP
OLN
ORP
ORN
100nF
100nF
VCCA VCCP
HDET
See application example in
Section 3.16 on page 19
VCCIO
Needed if IRQ
is not set to CMOS
IRQ
OCKAD
OCKDA
MasterClocks for
Other Digital Device
or for Digital Audio
Data Source
AD_SYNC
AD_DATA
AD_CK
AD_Fs
[8kHz-48kHz]
[88kHz-96kHz]
A/D
AD_Data
Audio Data
Interface
AD_Data Clock
To have a single bidirectional interface
connect:
AD_SYNC to DA_SYNC
AD_CK to DA_CK
DA_SYNC
DA_DATA
DA_CK
AMCK
DA_Fs
[8kHz-48kHz]
[88kHz-96kHz]
DA_Data
DA_Data Clock
D/A
Audio Data
Interface
100pF
System Clock
[4MHz-32MHz]
SDA/SDIN
SCLK
AS/CSB
CMOD
Data
I2C compat. Bus
Clock
I²C compat. Bus selected
100nF
VCCD
VCCIO
1µF 10µF
100nF
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