STW5095 Datasheet, PDF (10/69 Pages) STMicroelectronics – Low Power Asynchronous Stereo Audio Codec with Integrated Power Amplifiers

3 Functional Description
3 Functional Description
STw5095
3.1 Power supply
STw5095 can have different supply voltages for different blocks, to optimize performance,
power consumption and connectivity. See Operative supply voltage on page 50 for voltage
definition.
The correct sequence to apply supply voltage is to set first (and unset last) the digital I/O supply
(V_CCIO). The other supply voltages can be set in any order and can be disconnected
individually, if needed. Disconnection does not cause any harm to the device and no extra
current is pulled from any supply during this operation. Moreover if a voltage conflict is
detected, like V_CCA < V_CC (not allowed), simply all blocks connected to V_CCA are set to power
down and no extra current is pulled from supply.
When V_CCIO is set and V_CC (digital supply) is not set, all the digital output pins are in high
impedance state, while the digital inputs are disconnected to avoid power consumption for any
input voltage value between GND and V_CCIO. Before V_CC is disconnected the device has to be
reset (SWRES bit in CR30).
When the analog supply (V_CCA) is set and V_CC is not set, all the analog inputs are in high
impedance state.
The control registers are powered by VCC pin (digital supply) so if this pin is disconnected all
the information stored in control registers is lost. When the digital supply voltage is set, a
power-on-reset (POR) circuit sets all the registers content to the default value and then
generates an IRQ signal writing 1 in bits PORMSK and POREV in CR31 and CR32
respectively.
All supplies must be on during operation.
3.2 Device programming
STw5095 can be programmed by writing Control Registers with SPI or I²C compatible control
interface (both slave). The interface is always active, there is no need to have the master clock
running to program the device registers.
The choice between the two interfaces is done via an input pin (CMOD):
1. CMOD connected to GND: I²C compatible mode selected
The device address is selected with AS pin:
AS connected to GND: chip address 00110101(35hex) for reading, 00110100 (34hex) for writing
AS connected to V_CCIO: chip address 00110111(37hex) for reading, 00110110 (36hex) for writing
When this mode is selected control registers are accessed through pins:
SCLK (clock)
SDA (serial data out/in, open drain)
2. CMOD connected to V_CCIO: SPI compatible mode selected
When this mode is selected control registers are accessed through:
CSB (chip select, active low)
SCLK (clock)
SDIN (serial data in)
AD_OCK or DA_OCK or IRQ (serial data out, if selected)
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