ST10C167 Datasheet, PDF (61/65 Pages) STMicroelectronics – 16-BIT MCU WITH 32K BYTE ROM

ST10C167
XX - ELECTRICAL CHARACTERISTICS (continued)
Figure 24 : External bus arbitration, (regaining the bus)
2)
CLKOUT
HOLD
t₆₁
t₆₂
HLDA
t₆₂
t₆₂
t₆₃
BREQ
1)
t₆₅
CSx
(On P6.x)
t₆₇
Other
Signals
Notes 1. This is the last opportunity for BREQ to trigger the indicated regain-sequence.Even if BREQ is activated earlier, the regain-sequence
is initiated by HOLD going high. Please note that HOLD may also be deactivated without the ST10C167 requesting the bus.
2. The next ST10C167 driven bus cycle may start here.
XX.4.13 - High-speed synchronous serial interface (SSC) timing
Master mode
V_CC = 5V ±10%, V_SS = 0V, CPU clock = 25MHz, T_A = -40 to +125°C, C_L = 100pF
Symbol
Parameter
Max. Baud rate = 6.25M Baud
(<SSCBR> = 0001h)
Min.
Max.
Variable Baud rate
(<SSCBR>=0001h-FFFFh) _Unit
Min.
Max.
t₃₀₀ ^{CC SSC clock cycle time}
t₃₀₁ ^{CC SSC clock high time}
t₃₀₂ ^{CC SSC clock low time}
t₃₀₃ ^{CC SSC clock rise time}
t₃₀₄ ^{CC SSC clock fall time}
t₃₀₅ ^{CC Write data valid after shift edge}
t₃₀₆₁ ^{CC Write data hold after shift edge}
t_307p
SR Read data setup time before
latch edge, phase error
detection on (SSCPEN = 1)
t_308p ^{SR Read data hold time after latch}
edge, phase error detection on
(SSCPEN = 1)
t₃₀₇ ^{SR Read data setup time before}
latch edge, phase error
detection off (SSCPEN = 0)
t₃₀₈ ^{SR Read data hold time after latch}
edge, phase error detection off
(SSCPEN = 0)
160
70
70
–
–
–
-2
60
4TCL
40
0
160
8 TCL
262144 TCL ns
–
t₃₀₀/2 - 10
–
ns
–
t₃₀₀/2 - 10
–
ns
10
–
10
ns
10
–
10
ns
15
–
15
ns
–
-2
–
ns
–
2TCL+20
–
ns
–
4TCL
–
ns
–
40
–
ns
–
0
–
ns
Note 1. timing guaranteed by design.
61/65