L99DZ100G Datasheet, PDF (61/197 Pages) –

L99DZ100G, L99DZ100GP
Electrical specifications
Table 47. Inputs: CLK, DI (continued)
Symbol
Parameter
Test condition
Min. Typ. Max. Unit
C_in(1)
f_CLK
Input capacitance at
input CSN, CLK, DI and
PWM_1,2
SPI input frequency at
CLK
Guaranteed by design
15 pF
4 MHz
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
Symbol
t_CLK
t_CLKH
t_CLKL
t_{set_CSN}
t_{set_CLK}
t_{set_DI}
t_{hold_DI}
t_{r_in}
t_{f_in}
Table 48. DI, CLK and CSN timing
Parameter
Test condition
Min.
Clock period
250
Clock high time
100
Clock low time
100
CSN setup time, CSN low
before rising edge of CLK
150
CLK setup time, CLK high
before rising edge of CSN
150
DI setup time
25
DI hold time
25
Rise time of input signal DI,
CLK, CSN
Fall time of input signal DI,
CLK, CSN
Typ.
Max. Unit
ns
ns
ns
ns
ns
ns
ns
25 ns
25 ns
Note:
See Figure 16: SPI input timing.
Symbol
V_DOL
V_DOH
I_DOLK
C_DO
Parameter
Output low level
Output high level
3-state leakage
current
3-state input
capacitance
Table 49. Output: DO
Test condition
I_DO = -4 mA
I_DO = 4 mA
V_CSN = V1, 0 V < V_DO < V1
Guaranteed by design
Min.
V1 - 0.5
Typ.
Max. Unit
0.5 V
V
-10
10 μA
10
15 pF
Symbol
t_{r DO}
t_{f DO}
Parameter
DO rise time
DO fall time
Table 50. DO timing
Test condition
C_L = 50 pF; I_LOAD = -1 mA
C_L = 50 pF; I_LOAD = -1 mA
Min.
Typ. Max. Unit
25 ns
25 ns
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