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STM32F101XF Datasheet, PDF (60/117 Pages) STMicroelectronics – Single-cycle multiplication and hardware division
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Electrical characteristics
STM32F101xF, STM32F101xG
Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2)
Symbol
Parameter
Min
Max
Unit
th(Data_NWE) Data hold time after FSMC_NWE high
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low
tw(NADV) FSMC_NADV low time
1. CL = 15 pF.
2. Guaranteed by characterization results.
tHCLK
-
-
-
ns
0
ns
tHCLK + 1.5 ns
Figure 21. Asynchronous multiplexed NOR/PSRAM read waveforms
&3-#? .%
TV./%?.%
TW.%
T H.%?./%
&3-#?./%
&3-#?.7%
&3-#? !;=
&3-#? .",;=
&3-#? !$;=
TV!?.%
TV",?.%
T V!?.%
!DDRESS
T V.!$6?.%
TW.!$6
T W./%
!DDRESS
.",
TH!?./%
TH",?./%
TSU$ATA?.%
TSU$ATA?./%
$ATA
TH!$?.!$6
TH$ATA?.%
TH$ATA?./%
&3-#?.!$6
AIB
Table 33. Asynchronous multiplexed NOR/PSRAM read timings(1)(2)
Symbol
Parameter
Min
Max
Unit
tw(NE)
tv(NOE_NE)
tw(NOE)
th(NE_NOE)
tv(A_NE)
tv(NADV_NE)
tw(NADV)
th(AD_NADV)
FSMC_NE low time
FSMC_NEx low to FSMC_NOE low
FSMC_NOE low time
FSMC_NOE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
FSMC_AD (address) valid hold time after
FSMC_NADV high
7tHCLK + 0.5 7tHCLK + 2
ns
3tHCLK + 0.5 3tHCLK + 1.5 ns
4tHCLK – 1 4tHCLK + 1
ns
0.5
-
ns
-
0
ns
0
1
ns
tHCLK + 0.5
tHCLK + 2 ns
tHCLK
-
ns
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