M65KA512AB Datasheet, PDF (6/55 Pages) STMicroelectronics – 512Mbit (4 Banks x 8M x 16), 133 MHz Clock Rate, Bare Die, 1.8 V Supply, Low Power SDRAM

Description
1
Description
M65KA512AB
The M65KA512AB is a 512 Mbit Low Power Synchronous DRAM (SDRAM). The memory
array is organized as 4 Banks of 8,388,608 words of 16 bits each.
The LPSDRAM achieves low power consumption and high-speed data transfer using the
pipeline architecture.
The device architecture is illustrated in Figure 2: Functional block diagram. It uses Burst
mode to read and write data. It is capable of one, two, four, eight-word and full-page,
sequential and interleaved Burst.
To minimize current consumption during self-refresh operations, the M65KA512AB includes
three mechanisms configured via the Extended Mode Register:
● Automatic Temperature Compensated Self Refresh (ATCSR) used to adapt the refresh
time according to the operating temperature (see Table 5: Extended mode Register
definition)
● Partial Array Self Refresh (PASR) performs a limited refresh of part of the PSRAM
memory array. This area can be configured to half bank, a quarter of bank, one bank,
two banks or all banks. This mechanism allows to reduce the device Standby current by
refreshing only the part of the memory array that contains essential data.
● The Deep Power-Down (DPD) mode completely halts the refresh operation and
achieves minimum current consumption by cutting off the supply voltage from the
whole memory array.
The device is programmable through two registers, the Mode Register and the Extended
Mode Register:
● The Mode Register is used to select the CAS Latency, the Burst Type (sequential,
interleaved) and the Burst Length (1-, 2-, 4-, 8-word width or full page) through
programming the A6 to A4 bits, the A3 bit and the A2 to A0 bits, respectively (see
Table 4).
● The Extended Mode Register is used to program the low-power features (PASR,
ATCSR) and Driver Strength) to reduce the current consumption during the Self
Refresh operations. For more details, refer to Table 5: Extended mode Register
definition, and to Section 4.2: Extended Mode Register Set command.
6/55