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M65KA512AB Datasheet, PDF (27/55 Pages) STMicroelectronics – 512Mbit (4 Banks x 8M x 16), 133 MHz Clock Rate, Bare Die, 1.8 V Supply, Low Power SDRAM | |||
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M65KA512AB
DC and ac parameters
Table 10. DC characteristics 2
Symbol
Parameter
Test condition(1)
M65KA512AB
Unit
Max
IDD1(2) Operating current
CAS Latency = 2 Burst length = 1, one bank active
CAS Latency = 3 tRC ⥠tRC(min), IOL = 0 mA
70
mA
70
IDD2P Precharge Standby current in
IDD2PS Power-Down Mode
IDD2N
Precharge Standby current in
Non Power-Down Mode
IDD2NS
KE ⤠VIL(max), tK = tK(min)
KE ⤠VIL(max), tK = â
KE ⥠VIH (min), E ⥠VIH (min), tK =
tK(min)
Input signals changed once in 30 ns
All other pins ⥠VDD â 0.2 V or ⤠0.2 V
KE ⥠VIH (min), tK = â
Input signals are stable
0.8
mA
0.6
4.0
mA
2.0
IDD3P Active Standby current in
IDD3PS Power-Down Mode
IDD3N
Active Standby current in
Non Power-Down Mode
IDD3NS
KE ⤠VIL(max), tK = tK(min)
KE ⤠VIL(max), tK = â
3.0
mA
1.2
KE ⥠VIH (min), E ⥠VIH (min), tK= tK(min)
Input signals changed once in 30 ns
10
All other pins ⥠VDD â 0.2 V or ⤠0.2 V
mA
KE ⥠VIH (min), tK = â
7
Input signals are stable
IDD4(2) Burst Mode current
CAS Latency = 2 tK ⥠tK (min), IOL = 0 mA
CAS Latency = 3 All banks active
IDD5 Auto-Refresh current
IDD6 Self-Refresh current
IDD7
Standby current in Deep
Power-Down Mode
tRRC ⥠tRRC (min), All banks active
KE ⤠0.2 V
KE ⤠0.2 V
50
mA
85
90
mA
See Table 11 µA
10
µA
1. TJ = â30 to 85 °C.
2. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open.
Table 11. Self-Refresh current values in Normal Operating Mode
Memory array(1)
Temperature in °C
4 Banks
2 Banks
1 Bank
Unit
Typ
Max
Typ
70 ⤠TJ ⤠85
800
40 ⤠TJ ⤠70
550
â30 ⤠TJ ⤠40
300
1. VDD = 1.8 ± 0.1 V, VDDQ = 1.8 ± 0.1 V, VSSQ = 0 V.
Max
650
380
240
Typ
Max
490
µA
290
µA
210
µA
27/55
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