M41ST87W Datasheet, PDF (6/42 Pages) STMicroelectronics – 5.0, 3.3, or 3.0V, 1280 bit (160 x8) Secure Serial RTC and NVRAM Supervisor with Tamper Detection

M41ST87Y, M41ST87W
Figure 2. Logic Diagram
VCC VBAT
SCL
SDA
EX
RSTIN1
RSTIN2
WDI
PFI1
PFI2
TP1IN
TP2IN
M41ST87Y
M41ST87W
ECON
RST(1)
IRQ/OUT(1)
SQW/FT(2)
PFO1(2)
PFO2(2)
VOUT
F32k(1)
TPCLR
VSS
AI07023
Note: 1. Open drain output
2. Programmable output (Open drain or Full-CMOS)
Figure 3. 28-pin, 300mil SOIC (MX)
Connections
NF
NF
NF
NF
NC
NC
PFO2
SQW/FT
WDI
RSTIN1
RSTIN2
PFO1
PFI2
VSS
1
28
2
27
3
26
4
25
5
24
6
23
7 _M41ST87Y 22
8 _M41ST87W 21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
EX
IRQ/OUT
VOUT
TP2IN
PFI1
SCL
F32k
TP1IN
RST
TPCLR
SDA
ECON
VBAT
AI07025b
Note: No Function (NF) and No Connect (NC) pins should be tied
to VSS. Pins 1, 2, 3, and 4 are internally shorted together.
Table 1. Signal Names
E_CON
Conditioned Chip Enable Output
EX
External Chip Enable
IRQ/OUT⁽¹⁾
Interrupt/Out Output
(Open drain)
PFI₁
Power Fail Input 1
PFI₂
Power Fail Input 2
PFO₁₍₂₎
Power Fail Output 1
PFO₂₍₂₎
Power Fail Output 2
RST⁽¹⁾
Reset Output (Open Drain)
RSTIN1
Reset 1 Input
RSTIN2
Reset 2 Input
SCL
Serial Clock Input
SDA
Serial Data Input/Output
SQW/FT⁽²⁾
Square Wave Output/Frequency
Test
WDI
Watchdog Input
V_CC
Supply Voltage
V_OUT
Voltage Output
V_SS
Ground
F_32k(1)
32kHz Square Wave Output
(Open drain)
TP1_IN
Tamper Pin 1 Input
TP2_IN
Tamper Pin 2 Input
TP_CLR
Tamper Pin RAM Clear
V_BAT
Positive Battery Pin Input
NF⁽³⁾
No Function
NC⁽³⁾
No Connect
Note: 1. Open drain output
2. Programmable output (Open drain or Full-CMOS)
3. Should be connected to V_SS.
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