M41ST87W Datasheet, PDF (18/42 Pages) STMicroelectronics – 5.0, 3.3, or 3.0V, 1280 bit (160 x8) Secure Serial RTC and NVRAM Supervisor with Tamper Detection

M41ST87Y, M41ST87W
Tamper Detect Sampling (TDS1 and TDS2).
This bit selects between a 1Hz sampling rate or
constant monitoring of the Tamper Input Pin(s) to
detect a tamper event when the Normally Closed
switch mode is selected. This allows the user to re-
duce the current drain when the TEB_X Bit is en-
abled while the device is in battery backup (see
Table 4., page 18 and Figure 17., page 19). Sam-
pling is disabled if the TCM_X Bit is set to logic '1'
(Normally Open). In this case the state of the
TDS_X Bit is a “Don’t care.”
Note: The crystal oscillator must be “On” for sam-
pling to be enabled.
Tamper Current Hi/Tamper Current Lo (TCHI/
TCLO1 and TCHI/TCLO2). This bit selects the
strength of the internal pull-up or pull-down used
during the sampling of the Normally Closed condi-
tion. The state of the TCHI/TCLO_X Bit is a “Don’t
care” for Normally Open (TCM_X = '1') mode (see
Figure 18., page 19).
RAM Clear (CLR1 and CLR2). When either of
these bits and the TEB_X Bit are set to a logic '1,'
the internal 128 bytes of user RAM (see Figure
15., page 17) will be cleared to all zeros in the
event of a tamper condition. The 128 bytes of user
RAM will be deselected (invalid data will be read)
until the corresponding TEB_X Bit is reset to '0.'
RAM Clear External (CLR1_EXT and CLR2_EXT).
When either of these bits are set to a logic '1' and
the TEB_X Bit is also set to logic '1,' the external
SRAM will be cleared and the RST output enabled
(see Figure 15., page 17 and Figure
20., page 21).
Note: The reset output resulting from a tamper
event will be the same as a reset resulting from a
power-down condition, a watchdog time-out, or a
manual reset (RSTIN1 or RSTIN2).
This is accomplished by forcing TP_CLR high, which
if used to control the inhibit pin of the DC regulator
(see Figure 20., page 21) will also switch off V_OUT,
depriving the external SRAM of power to the V_CC
pin. V_OUT will automatically be disconnected from
the battery if the tamper occurs during battery
back-up (see Figure 19., page 20). By inhibiting
the DC regulator, the user will also prevent other
inputs from sourcing current to the external SRAM,
allowing it to retain data.
The user may optionally connect an inverting
charge pump to the V_CC pin of the external SRAM
(see Figure 20., page 21). Depending on the pro-
cess technology used for the manufacturing of the
external SRAM, clearing the memory may require
varying durations of negative potential on the V_CC
pin. This device configuration will allow the user to
program the time needed for their particular appli-
cation. Control Bits CLRPW0 and CLRPW1 deter-
mine the duration TP_CLR will be enabled (see
Figure 19., page 20 and Table 5., page 20).
Note: When using the inverting charge pump, the
user must also provide isolation in the form of two
additional small-signal power MOSFETs. These
will isolate the V_OUT pin from both the negative
voltage generated by the charge pump during a
tamper condition, and from being pulled to ground
by the output of the charge pump when it is in shut-
down mode (SHDN = logic low). The gates of both
MOSFETs should be connected to TP_CLR as
shown in Figure 20., page 21. One n-channel en-
hancement MOSFET should be placed between
the output of the inverting charge pump and the
V_OUT of the M41ST87. The other MOSFET should
be an enhancement mode p-channel, and placed
between V_OUT of the M41ST87 and V_CC of the ex-
ternal SRAM. When TP_CLR goes high after a
tamper condition occurs, the n-channel MOSFET
will turn on and the p-channel will turn off. During
normal operating conditions, TP_CLR will be low
and the p-channel will be on, while the n-channel
will be off.
Table 4. Tamper Detection Current (Normally Closed - TCM_X = '0')
TDS_X
TCHI/TCLO_X
Tamper Circuit Mode
Current at 3.0V (typ)^(1,2)
0
0
Continuous Monitoring / 10MΩ pull-up/-down
0.3
0
1
Continuous Monitoring / 1MΩ pull-up/-down
3.0
1
0
Sampling (1Hz) / 10MΩ pull-up/-down
0.3
1
1
Sampling (1Hz) / 1MΩ pull-up/-down
3.0
Note: 1. When calculating battery lifetime, this current should be added to I_BAT current listed in Table 17., page 37.
2. Per Tamper Detect Input
Unit
µA
µA
nA
nA
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