M34F04 Datasheet, PDF (6/20 Pages) STMicroelectronics – 4Kbit Serial I2C Bus EEPROM With Hardware Write Control on Top Half of Memory

M34F04
Figure 5. I²C Bus Protocol
SCL
SDA
START
Condition
SDA
Input
SDA
Change
STOP
Condition
SCL
SDA
1
2
3
MSB
START
Condition
7
8
9
ACK
SCL
SDA
1
2
3
MSB
7
8
9
ACK
STOP
Condition
AI00792B
Table 2. Device Select Code
Device Type Identifier¹
Chip Enable^2,3
RW
b7
b6
b5
b4
b3
b2
b1
b0
Device Select Code
1
0
1
0
E2
E1
Note: 1. The most significant bit, b7, is sent first.
2. E1 and E2 are compared against the respective external pins on the memory device.
3. A8 represents most significant bits of the address.
A8
RW
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