HDMI2C1-14HD Datasheet, PDF (6/32 Pages) STMicroelectronics – HPD pull down and signal conditioning

Application information
HDMI2C1-14HD
In case the application is set in stand-by mode, the +5 V main supply of the application is
generally powered off in order to reduce as much as possible the global power
consumption. The CEC driver can be the only device still working in low power mode,
allowing a wake up of the whole application through the CEC line. When the main power
supply +5 V is switched off, and if the CEC bus is still active (V_{DD_CEC} power in on state),
the HDMI2C1-14HD keeps the CEC bus working properly while all other outputs of the
component are put in high impedance mode.
The CEC output (cable side) integrates a protection against ESD which is compliant with
IEC61000-4-2 standard, level 4 (8kV contact).
2.2
DDC functional block description
The DDC bus is described in the HDMI^™ standards as the Display Data Channel. The
topology corresponds to an I2C bus that must be compliant with the I2C bus specification
version 5 (October 2012). The DDC bus is made of 2 lines: data line (SDA) and clock line
(SCL). It is used to create a point to point communication link from the source to the sink.
EEDID and HDCP protocols are flowing through this link, making this I2C communication
channel a key element in the HDMI^™ application.
The DDC block integrated in the HDMI2C1-14HD allows a bidirectional communication
between the cable and the ASIC. It is fully compliant with the HDMI^™ 2.0 standard and its
CTS, and with the I2C bus specification version 2.1. It is shifting the 5V voltage from the
cable (V_{5V_OUT}) down to the ASIC voltage level (V_{DD_IC}) that can be as low as 1.8 V. The
Figure 5 shows the functional diagram of the DDC block integrated in the HDMI2C1-14HD
device.
Figure 5. DDC bus functional diagram (SCL and SDA lines)
VDD_IC
decoupling
capacitance
VDD_IC
HDMI
ASIC
SCL_IC
SDA_IC
+5V
VDD_5V
UVLO
Enable
reshaping
circuit
Drive
5V_OUT
VDD_5V
5V_OUT
SCL
SDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
17
16
19
18
HDMI
connector
The Figure 6 illustrates the electrical parameter of the DDC block specified in Table 8.
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DocID023674 Rev 2