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STW4810_0709 Datasheet, PDF (53/79 Pages) STMicroelectronics – Power management for multimedia processors
Electrical and timing characteristics
5.3.4
Table 38. VCORE DC/DC step-down converter (continued)
Symbol
Description
Test conditions
Min.
Typ.
VCORE regulator in sleep mode (SLEEP= ‘1’)
VBAT
VRIPPLE
Input power supply Battery voltage
VCORE output
voltage ripple
2.7
3.6
10
LIR
LDR
IOUT
Line regulation
Load regulation
VCORE output
current
VBAT: [2.7; 4.8]V
IOUT: [0.1; 5] mA
PEFF
Power efficiency
VBAT= 3.6 V
IOUT: [0.1; 5] mA
85
IQ
Quiescent current IOUT = 0 mA
20
LIRT
Transient line
regulation
Δ VBAT= 300 mV
tR = tF = 10 µs
7
1. Guaranteed by design
2. Guaranteed by design
VIO_VMEM DC/DC step-down converter
Table 39. VIO_VMEM DC/DC step-down converter
Symbol
Description
Test conditions
Min.
VIO_VMEM regulator in normal mode (SLEEP = ‘0’)
VBAT
Input power supply Battery voltage
2.7
VOUT
Output voltage (1)
-3%
VRIPPLE Output ripple
LIR
LDR(2)
Line regulation
Load regulation
VBAT: [2.7; 4.8]V
IOUT: [0.1; 600] mA
IOUT
Output current
PEFF
Power efficiency
VBAT = 3.6 V,
VIO = 1.8 V
IOUT= 100 mA
ISHORT
Short circuit
current limitation(2)
0.9
IQ
Quiescent current IOUT = 0 mA
PSRR(2)
Power supply
rejection
Vpp = 0.3 V
[0; 20] kHz
40
LIRT
LDRT
Transient line
regulation
Transient load
regulation
ΔVBAT = 300 mV
tR = tF = 10 µs
IOUT= [1; 600] mA
tR = tF = 100 ns
Typ.
3.6
1.8
10
90
1.2
130
7
70
STw4810
Max.
Units
4.8
V
mVpp
10
mV
10
mV
5
mA
%
30
µA
mV
Max.
Units
4.8
+3%
10
10
600
V
V
mVpp
mV
mV
mA
%
1.4
A
250
µA
dB
mV
mV
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