STW4810_0709 Datasheet, PDF (26/79 Pages) STMicroelectronics – Power management for multimedia processors

STw4810
Functional description
USB interrupt source register
Table 13. USB Interrupt source register (address = 08h)
Register
7
6
5
4
3
2
Bit name
cr_int
bdis_
acon
id_float
dn_hi
id_gnd_
forced
dp_hi
Type
R
R
R
R
R
R
1
sess_
vld
R
0
vbus_
vld
R
Bits
Name
7 cr_int
6 bdis_acon
5 id_float
4 dn_hi
3 id_gnd_forced
2 dp_hi
1 sess_vld
0 vbus_vld
USB latch register
Value
Settings
0 Inactive
1 DP ball is above the carkit interrupt threshold
0
Inactive
1
Set when bdis_acon_en is set, and transceiver
asserts dp_pullup after detecting B-device
disconnect.
0 _Inactive
1 ID ball floating
0 Inactive
1 _{DN ball is high}
0 Inactive
1 ID ball grounded
0 _Inactive
1 DP asserted during SRP,
0 Session valid comparator threshold <0.8V or >4.4V
1 _{0.8V < Session valid comparator threshold < 4.4V}
0 A-device VBUS valid comparator threshold <4.4V
1 A-device VBUS valid comparator threshold >4.4V
Default
0
0
0
0
0
0
0
0
Table 14. USB interrupt latch registers (address = 0Ah set and 0Bh clearh)
Register
7
6
5
4
3
2
1
0
Bit name
cr_int
bdis_
acon
id_float
dn_hi
id_gnd_
forced
dp_hi
sess_ vbus_
vld
vld
Default
0
0
0
0
0
0
0
0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
USB interrupt latch register bits indicate which sources have generate an interrupt.
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