TDA8204B Datasheet, PDF (5/12 Pages) STMicroelectronics – NICAM DECODER

TDA8204B
FUNCTION DESCRIPTION
The TDA8204B is partitioned into 6 major parts
shown in the block diagram.
The NICAM Decoder performs data and sound
recovery from the signals specified in
EBU SPB 424. The expanded digital audio signals
(14-bit) are made available at the digital audio
interface (I²S) in a serial multiplex of left and right
channels. They are also processed by a 4 times
upsampling digital filter and noise shaper which
results in a high speed digital data stream at the
output pins DACDL/DACDR. This data stream can
be applied to the 1-bit D-A convertors contained in
the TDA8205.
The TDA8204B is I²C bus controlled and provides
control over the functions of the TDA8205 by
means of a serial inter-chip bus.
1 - NICAM Decoder
1.1 - BLOCK DIAGRAM (see Figure 3)
1.2 - DESCRIPTION
NICAM frame alignment requires searching out a
frame alignment word (FAW) and a 16 frame se-
quence conveyed by C0 bit. Because of noise,
interferences, errors in the incoming NICAM Data,
aliases of the FAW, a robust scheme is imple-
mented. It ensures the decoder will align, and stay
aligned, to signals beyond the limit of maximum
useable error rate. Thanks to a 511 bit PRBS syn-
chronized by the recovered clock and a modulo 2
adder, original data are recovered. This data
stream can be processed externaly for de-encryp-
tion in Pay TV applications using descrambled data
Pins DDO, DDI.
To allow simultaneous reading and writing of
mono/stereo samples, de-interleaved data frames
are stored in a 3 page RAM.
Figure 3 : NICAM Decoder Block Diagram
The 10-bit input audio samples are expanded to
14-bit using scale factor bits according to NICAM
decoding rules. Samples in error by the parity
check are replaced by interpolated one or re-
peated.
Mute is set according to an error counter when the
error rate exceeds error rate limit (ERL) and reset
when the error rate is below ERL/4.
Application control information (bit C1, C2, C3, C4)
is recovered by majority decision logic over 16
frames. the C1, C2, C3 , C4 bits can be read in SR0
register and are set on the C1, C2, C3, C4 pins
according to the state of bit 0 (BEA) of the CR2
register.
2 - Digital Filter and Noise Shaper
A digital filter performs 4X upsampling in two
stages. The main FIR 2x upsampler is followed by
a smaller 2x FIR upsampler. Digital upsampling
means a much simpler post-DAC reconstruction
filter can be used thus saving on external compo-
nent count and cost.
A noise shaper converts the samples from the
digital filter into two high speed serial bitstreams
which can be applied to the DACs in the TDA8205.
3 - I²S Bus
A standard three-wire interface, conforming to the
I²S bus protocol, is provided, allowing connection
of an external DAC or DAT interface. Audio samples
contain 14-bit, so 16-bit DACs will pad the two LSBs
with 0. The word select clock operates at 32kHz
and the serial clock at 896kHz.
By setting SDI bit of CR2 to 1, the I²S interface can
receive the digital I²S sound. This prevents dupli-
cating the dual D/A converter.
28
27 21 20 19 18 6
MAJORITY
LOGIC
NDI 39
PDV 30
DV 33
FID 29
ADV 31
DESCRAMBLER
FRAME
CONTROL
3 PAGE
RAM
ADDRESS
GENERATOR
23
25
SCALE FACTOR
RECOVERY
EXPANDER
ERROR
COUNTER
CONCEAL
AND MUTE
TO FILTER
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