STE12PS Datasheet, PDF (5/44 Pages) STMicroelectronics – 12 channel integrated PSE line manager

STE12PS
2
Pin description
Pin description
Table 1. Analog pins description
Pin name
I/O
Function
IDET_HVLV
O
Anti-aliasing filter capacitor to be connected between the analog input and
ground to improve ADC noise performance. C = 180pF.
IMON_HVLV
O
Anti-aliasing filter capacitor to be connected between the analog input and
ground. C = 180pF.
Vbat_mon
O
Anti-aliasing filter capacitor to be connected between the analog input and
ground. C = 100nF.
Vbatref
O
Anti-aliasing filter capacitor to be connected between the analog input and
ground. C = 100nF.
I_REF
) ^CDETSLOW
t(s ^RSENSE
uc VDRIVE
rod ^SFTSTR
P _FB
te _Pn
ole _ACSn
bs _SPn
) ^{- O SSRPn}
ct(s _FSRPn
rodu ^RMONF
te ^{P RMONS}
le _RREF
so _{CLK_GEN1}
Ob^CLK_GEN2
O
Anti-aliasing filter capacitor to be connected between the analog input and
ground. C = 180pF.
O
Detection rise/fall time capacitor (up to 25nF). Tr/f can be set from 1ns to 4ms.
O
SMPS precision, external, current limiting reference resistor: 100mΩ
O
External p-channel MOSFET gate driving voltage for SMPS. It provides a
square wave with VL as upper limit and (VL-10V) as lower limit voltage.
O
Switched Mode Power Supply (SMPS) soft start capacitor, 200nF.
IO
SMPS feedback pin, Cfb = 2.2nF
O
Power DMOS device drain, if DMOS is turned-on, channel “n” where n = 1,…12
is activated.
O
It provides a 50Hz AC disconnection signal for port “n”, n = 1, … 12.
I
Detection classification and AC disconnection sensing port “n”, n = 1, … 12.
Line current to the monitoring resistor for channel “n”, n = 1,… 12. Allowed
I
values are 0.523, 1.05, 1.58 and 2.1ohms (see also SENSPROG preset pins).
Sensing pin.
O
Source terminal for power DMOS connected to the sense resistor for channel
“n”, n = 1,… 12, a “forcing” pin.
O
Mirror monitoring resistance (500 × R_sense) pin to let internal ADC evaluate line
currents. Forcing pin.
O
Mirror monitoring resistance (500 × R_sense) pin to let internal ADC evaluate line
currents. A “sensing” pin.
I
Reference bias resistor: 18.7kΩ
I
Crystal oscillator pin1 for high performance clock generation.
I
Crystal oscillator pin2 for high performance clock generation.
MCLK
O
Master clock output for multi device configuration.
CLK_GEN3
I
Low profile clock input pin or clock input pin in multi-device configuration.
ACin
I
50Hz sinusoidal input
ACout
O
50Hz sinusoidal output, internally generated
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