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STD4N80K5 Datasheet, PDF (5/23 Pages) STMicroelectronics – Ultra low gate charge
STD4N80K5, STF4N80K5, STP4N80K5, STU4N80K5
Electrical characteristics
Table 6. Switching times
Symbol
Parameter
Test conditions
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
Turn-off-delay time
Fall time
VDD = 400 V, ID = 1.5 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 18)
Min. Typ. Max. Unit
- 16.5 - ns
- 15
- ns
- 36
- ns
- 21
- ns
Symbol
Table 7. Source drain diode
Parameter
Test conditions
ISD
ISDM (1)
VSD (2)
Source-drain current
Source-drain current (pulsed)
Forward on voltage
ISD = 3 A, VGS = 0
trr
Qrr
IRRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 3 A, di/dt = 100 A/µs
VDD= 60 V
(see Figure 20)
trr
Qrr
IRRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 3 A, di/dt = 100 A/µs
VDD= 60 V TJ = 150 °C
(see Figure 20)
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Min. Typ. Max. Unit
-
3A
12 A
-
1.5 V
- 242
ns
- 1.42
µC
- 12
A
- 373
ns
- 1.98
µC
- 10.5
A
Table 8. Gate-source Zener diode
Symbol
Parameter
Test conditions
V(BR)GSO
Gate-source breakdown
voltage
IGS= ± 1 mA, ID=0
Min. Typ. Max. Unit
30
-
V
The built-in back-to-back Zener diodes have been specifically designed to enhance the ESD
capability of the device. The Zener voltage is appropriate for efficient and cost-effective
intervention to protect the device integrity. These integrated Zener diodes thus eliminate the
need for external components.
DocID025105 Rev 3
5/23
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