M28F101 Datasheet, PDF (5/23 Pages) STMicroelectronics – 1 Mb 128K x 8, Chip Erase FLASH MEMORY

Table 6. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
SRAM Interface Levels
≤ 10ns
0 to 3V
1.5V
M28F101
EPROM Interface Levels
≤ 10ns
0.45V to 2.4V
0.8V and 2V
Figure 3. AC Testing Input Output Waveform
SRAM Interface
3V
0V
EPROM Interface
2.4V
0.45V
1.5V
2.0V
0.8V
AI01275
Figure 4. AC Testing Load Circuit
1.3V
1N914
DEVICE
UNDER
TEST
3.3kΩ
OUT
CL = 30pF or 100pF
CL = 30pF for SRAM Interface
CL = 100pF for EPROM Interface
CL includes JIG capacitance
AI01276
Table 7. Capacitance ⁽¹⁾ (T_A = 25 °C, f = 1 MHz )
Symbol
Parameter
Test Condition
C_IN
Input Capacitance
V_IN = 0V
C_OUT
Output Capacitance
Note: 1. Sampled only, not 100% test.ed
V_OUT = 0V
Min
Max
Unit
6
pF
12
pF
READ/WRITE MODES (cont’d)
A write to the command register is made by bringing
W Low while E is Low. The falling edge of W latches
Addresses, while the rising edge latches Data,
which are used for those commands that require
address inputs, command input or provide data
output.
The supply voltage VCC and the program voltage
V_PP can be applied in any order. When the device
is powered up or when VPP is ≤ 6.5V the contents
of the command register defaults to 00h, thus
automatically setting-up Read operations. In addi-
tion a specific command may be used to set the
command register to 00h for reading the memory.
The system designer may chose to provide a con-
stant high V_PP and use the register commands for
all operations, or to switch the VPP from low to high
only when needing to erase or program the mem-
ory. All command register access is inhibited when
V_CC falls below the Erase/Write Lockout Voltage
(V_LKO) of 2.5V.
If the device is deselected during Erasure, Pro-
gramming or Verification it will draw active supply
currents until the operations are terminated.
The device is protected against stress caused by
long erase or program times. If the end of Erase or
Programming operations are not terminated by a
Verify cycle within a maximum time permitted, an
internal stop timer automatically stops the opera-
tion. The device remains in an inactive state, ready
to start a Verify or Reset Mode operation.
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