M27W801 Datasheet, PDF (5/16 Pages) STMicroelectronics – 8 Mbit 1Mb x8 Low Voltage UV EPROM and OTP EPROM

M27W801
Table 7. Read Mode DC Characteristics ⁽¹⁾
(T_A = –40 to 85 °C; V_CC = 2.7V to 3.6V; V_PP = V_CC)
Symbol
Parameter
Test Condition
Min
I_LI
Input Leakage Current
I_LO Output Leakage Current
I_CC Supply Current
I_CC1 Supply Current (Standby) TTL
0V ≤ V_IN ≤ V_CC
0V ≤ V_OUT ≤ V_CC
E = V_IL, GV_PP = V_IL, I_OUT = 0mA,
f = 5MHz, V_CC ≤ 3.6V
E = V_IH
I_CC2 Supply Current (Standby) CMOS
I_PP Program Current
V_IL
Input Low Voltage
E > V_CC – 0.2V, V_CC ≤ 3.6V
V_PP = V_CC
–0.6
V_IH ^{(2) Input High Voltage}
0.7 V_CC
V_OL Output Low Voltage
I_OL = 2.1mA
V_OH Output High Voltage TTL
I_OH = –1mA
3.6
Note: 1. V_CC must be applied simultaneously with or before V_PP and removed simultaneously or after V_PP.
2. Maximum DC voltage on Output is V_CC +0.5V.
Max
±10
±10
15
1
15
10
0.2 V_CC
V_CC + 0.5
0.4
Unit
µA
µA
mA
mA
µA
µA
V
V
V
V
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, the product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, I_CC, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
the transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output. The associated transient voltage peaks
can be suppressed by complying with the two line
output control and by properly selected decoupling
capacitors. It is recommended that a 0.1µF ceram-
ic capacitor be used on every device between V_CC
and V_SS. This should be a high frequency capaci-
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7µF bulk electrolytic capacitor should be
used between V_CC and V_SS for every eight devic-
es. The bulk capacitor should be located near the
power supply connection point. The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
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