HCC4031B Datasheet, PDF (5/12 Pages) STMicroelectronics – 64-STAGE STATIC SHIFT REGISTER

HCC/HCF4031B
DYNAMIC ELECTRICAL CHARACTERISTICS (T _amb = 25°C, C_L = 50pF, R_L = 200kΩ,
typical temperature coefficient for all V_DD values is 0.3%/°C, all input rise and fall times = 20ns)
Symbol
Parameter
t_PHL ,
Propagation Delay Time :
t _{PL H}, t _{PL H} Clock to Q,
Clock to Q
Test Conditions
V al ue
V _{D D} (V) Min. Typ. Max.
5
250 500
10
110 220
15
90 180
Unit
ns
t_PHL ,
Propagation Delay Time :
t _{PL H}, t _PHL Clock to Q’
Clock to Q
5
190 380
10
80 160
ns
15
65 130
Clock to CL_D
5
100 200
10
50 100
ns
t _{THL ’}, t_{T L H} Transition Time :
(any output, except Qt_THL)
15
40 80
5
100 200
10
50 100
ns
t_{T HL}
Q,
15
40 80
5
50 100
10
25 50
ns
15
20 40
t _{s e t u p} Data Setup Time
5
30 60
10
15
30
ns
15
10 20
t _{h o ld} Data Hold Time
5
30 60
10
15 30
ns
15
10 20
t_W
Clock Pulse Width
f_max Maximum Clock Input
Frequency**
t_r, t_f Clock Input Rise or Fall Time*
5
120 240
10
50 100
ns
15
40 80
5
2
4
10
5
10
MHz
15
6
12
5
1000
10
1000 µs
15
200
* If more than one unit is cascaded in the parallel clocked application, trCL should be made less than or equal to the sum of
the propagation delay at 50pF and the transmition time of the output driving stage.
* * Maximum Clock Frequency for Cascaded Units;
a) Using Delayed Clock Feature in Recirculation Mode :
fmax =
(n-1)
CLD
prop.
delay
1
+
Q
prop.
delay
+
set-up
ti mewhere
n
=
nimber
of
packages
b) Not Usng Delaye Clock :
fmax =
1
propagation delay + set-up time
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