STM32L471XX Datasheet, PDF (47/218 Pages) STMicroelectronics – Batch acquisition mode

STM32L471xx
Functional overview
3.25
Inter-integrated circuit interface (I2C)
The device embeds 3 I2C. Refer to Table 11: I2C implementation for the features
implementation.
The I²C bus interface handles communications between the microcontroller and the serial
I²C bus. It controls all I²C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
• I²C-bus specification and user manual rev. 5 compatibility:
– Slave and master modes, multimaster capability
– Standard-mode (Sm), with a bitrate up to 100 kbit/s
– Fast-mode (Fm), with a bitrate up to 400 kbit/s
– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
– Programmable setup and hold times
– Optional clock stretching
• System Management Bus (SMBus) specification rev 2.0 compatibility:
– Hardware PEC (Packet Error Checking) generation and verification with ACK
control
– Address resolution protocol (ARP) support
– SMBus alert
• Power System Management Protocol (PMBus^TM) specification rev 1.1 compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming. Refer to
Figure 3: Clock tree.
• Wakeup from Stop mode on address match
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability
Table 11. I2C implementation
I2C features⁽¹⁾
I2C1
Standard-mode (up to 100 kbit/s)
X
Fast-mode (up to 400 kbit/s)
X
Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)
X
Programmable analog and digital noise filters
X
SMBus/PMBus hardware support
X
Independent clock
X
Wakeup from Stop 0 / Stop 1 mode on address match
X
Wakeup from Stop 2 mode on address match
-
1. X: supported
I2C2
X
X
X
X
X
X
X
-
I2C3
X
X
X
X
X
X
X
X
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