STM32L471XX Datasheet, PDF (146/218 Pages) STMicroelectronics – Batch acquisition mode

Electrical characteristics
STM32L471xx
Table 63. ADC characteristics^{(1) (2)} (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
t_LATRINJ
Trigger conversion
latency Injected channels
aborting a regular
conversion
CKMODE = 00
CKMODE = 01
CKMODE = 10
CKMODE = 11
t_s
Sampling time
f_ADC = 80 MHz
-
t_{ADCVREG_STUP}
ADC voltage regulator
start-up time
-
t_CONV
Total conversion time
(including sampling time)
f_ADC = 80 MHz
Resolution = 12 bits
Resolution = 12 bits
I_DDA(ADC)
ADC consumption from
the V_DDA supply
I_{DDV_S}(ADC)
ADC consumption from
the V_REF+ single ended
mode
I_{DDV_D}(ADC)
ADC consumption from
the V_REF+ differential
mode
fs = 5 Msps
fs = 1 Msps
fs = 10 ksps
fs = 5 Msps
fs = 1 Msps
fs = 10 ksps
fs = 5 Msps
fs = 1 Msps
fs = 10 ksps
2.5
3
3.5
-
-
3.0
-
-
3.25
1/f_ADC
-
-
3.125
0.03125
-
8.00625
µs
2.5
-
640.5
1/f_ADC
-
-
20
µs
0.1875
-
8.1625
ts + 12.5 cycles for
successive approximation
= 15 to 653
-
730
830
-
160
220
-
16
50
-
130
160
-
30
40
-
0.6
2
-
260
310
-
60
70
-
1.3
3
µs
1/f_ADC
µA
µA
µA
1. Guaranteed by design
2.
The I/O
V_DDA <
analog switch voltage booster
2.4V). It is disable when V_DDA
is
≥
enable
2.4 V.
when
V_DDA
<
2.4
V
(BOOSTEN
=
1
in
the
SYSCFG_CFGR1
when
3. V_{ReRfEeFr +tocS}an_ecb_te_ionint₄e_:r_Pna_inll_oy_uc_tson_an_ne_dc_pte_ind _dto_esV_cDrDipAtioa_nndfoVr _{RfuErFth- ecar} ndebteaiilns.ternally connected to V_SSA, depending on the package.
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