STA015_04 Datasheet, PDF (46/55 Pages) STMicroelectronics – MPEG 2.5 LAYER III AUDIO DECODER WITH ADPCM CAPABILITY

STA015 STA015B STA015T
6.3 TIMING DIAGRAMS
6.3.1 Audio DAC Interface
a) OCLK in output. The audio PLL is used to clock the DAC
OCLK (OUTPUT)
SDO
t_sdo
SCKT
t_sckt
LRCLK
t_lrclk
tsdo = 3.5 + pad_timing (Cload_SDO) - pad_timing (Cload_ OCLK)
tsckt = 4 + pad_timing (Cload_SCKT) - pad_timing (Cload_ OCLK)
tlrckt = 3.5 + pad_timing (Cload_LRCCKT) - pad_timing (Cload_ OCLK)
D98AU969
Pad-timing versus load
Load (pF)
25
50
75
100
Pad_timing
2.90ns
3.82ns
4.68ns
5.52ns
Cload_XXX is the load in pF on the XXX output. pad_timing (Cload_XXX) is the propagation delay added
to the XXX pad due to the load.
b) OCLK in input.
OCLK (INPUT)
t_hi
t_lo
SDO
SCKT
LRCLK
46/55
t_sdo
t_sckt
t_lrclk
t_oclk
D98AU970