English
Language : 

STW82103B Datasheet, PDF (45/67 Pages) STMicroelectronics – RF down converter with embedded integer-N synthesizer
STW82103B
I2C bus interface
9.4
Device calibration through the I2C interface
9.4.1
9.4.2
VCO calibration procedure (I2C interface)
The calibration of the VCO center frequency is activated by setting the SERCAL bit of the
MUTE & CALIBRATION register to ’1’.
To program the device ensuring a correct VCO calibration, the following procedure is
required before every channel change:
1. Program all the Registers using a multi-byte write sequence with the desired setting:
– Functional Mode
– B and A counters
– R counter
– VCO amplitude
– Charge Pump
– Prescaler Modulus
– DAC
– Mixer and LO Control
– all bits of the MUTE & CALIBRATION Register (0x05) set to ’0’.
2. Program the MUTE & CALIBRATION register using a single-byte write sequence (sub-
address 0x05) with the SERCAL bit set to ’1’.
The maximum allowed PFD frequency (FPFD) to perform the calibration process is 1 MHz. If
the desired FPFD is higher than 1 MHz the following steps are needed:
3. Perform all the step of the above calibration procedure programming the desired VCO
frequency with a proper setting of R, B and A counter so that FPFD results lower than
1 MHz.
4. Once calibration is completed, program all the Registers by using a multi-byte write
sequence (Functional Mode, B and A counters, R counter, VCO amplitude, Charge
Pump, Prescaler Modulus, DAC, Mixer and LO Control) with the proper settings for the
desired VCO and PFD frequencies.
Power ON sequence (I2C interface)
At power-on the device is configured in power-down mode.
In order to guarantee correct setting of the internal circuitry after the power on, the following
steps must be followed:
1. Power up the device
2. Provide the Reference clock
3. Implement the first programming sequence with a proper delay time between the STOP
condition of the multi-byte write sequence and that of the single-byte write sequence
(see Figure 20). The Tdelay value must respect the following condition:
Tdelay > 1023
×
----1-----
Fref
Fref is the reference clock frequency.
Doc ID 018517 Rev 2
45/67