L6751B Datasheet, PDF (44/58 Pages) STMicroelectronics – Digitally controlled dual PWM for Intel VR12 and AMD SVI

Efficiency optimization
L6751B
Note:
Figure 13 allows the efficiency improvements with DPM/GDC enabled to be compared with
respect to the standard solution.
Systems supporting S3 power state may have the VDRV supplied by an OR-ing connection
between 5 Vsby and 12 V or different supply voltage for S0. It is recommended to connect
closely, between the VDRV and VCC5 pins, the OR-ing diode connecting VDRV to the 5
Vsby.
Figure 13. Efficiency performance with and without enhancements (DPM, GDC).
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Doc ID 024028 Rev 1