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L6751B Datasheet, PDF (31/58 Pages) STMicroelectronics – Digitally controlled dual PWM for Intel VR12 and AMD SVI
L6751B
Output voltage positioning
Figure 7 shows the current sense circuit used to implement the load-line. The current flow-
ing across the inductor(s) is read through the R-C filter across the CSxP and CSxN pins. RG
programs a trans-conductance gain and generates a current ICSx proportional to the current
of the phase. The sum of the ICSx current, with proper gain eventually adjusted by the
PMBus commands, is then sourced by the FB pin (IDROOP). RFB gives the final gain to pro-
gram the desired load-line slope (Figure 6).
Time constant matching between the inductor (L / DCR) and the current reading filter (RC)
is required to implement a real equivalent output impedance of the system, therefore avoid-
ing over and/or undershoot of the output voltage as a consequence of a load transient. The
output voltage characteristic vs. load current is then given by:
Equation 4
VOUT = VID – RFB ⋅
IDROOP = VID – RFB ⋅
D-----C-----R---
RG
⋅
IOUT = VID – RLL ⋅
IOUT
where RLL is the resulting load-line resistance implemented by the multi-phase section.
The RFB resistor can be then designed according to the RLL specifications as follows:
Equation 5
RFB = RLL ⋅
---R-----G-----
DCR
Caution: When in DDR mode, and enabled, droop current has a scaling factor equal to 1/4. All the
above equations must be scaled accordingly.
6.4
Single-phase section - disable
The single-phase section can be disabled by pulling high the SPWM pin. The related
command is rejected.
6.5
Single-phase section - current reading
The single-phase section performs the same differential current reading across DCR as the
multi-phase section. According to Section 6.2, the current that flows from the SCSN pin is
then given by the following equation (see Figure 7):
Equation 6
ISCSN
=
D-----C----R---
RSG
⋅
ISOUT = ISDROOP
6.6
Single-phase section - defining load-line
This method introduces a dependence of the output voltage on the load current recovering
part of the drop due to the output capacitor ESR in the load transient. Introducing a depen-
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