STLUX Datasheet, PDF (42/126 Pages) STMicroelectronics – Digital controllers for lighting and power conversion applications with up to 6 programmable PWM generators, 96 MHz PLL, DALI

I/O multifunction signal configuration
STLUX
MSC_IOMXP1 (Port P1 I/O MUX control register)
Table 10. MSC_IOMXP1 (Port P1 I/O MUX control register)
Offset: 0x2B
Default value: 0x3F
7
6
RFU
r
5
Sel_P15⁽¹⁾, ⁽²⁾
4
Sel_P14⁽¹⁾
3
Sel_P13
r/w
2
Sel_P12
1
Sel_P11
0
Sel_P10
1. Not available on the STLUX285A; these bits are set to 1 after reset, must be cleared by SW during the IC
device initialization phase and during register write operations.
2. Not available on the STLUX325A; these bits are set to 1 after reset, must be cleared by SW during the IC
device initialization phase and during register write operations.
The Port1 I/O multifunction signal configuration register (for functionality description refer to
Section 7.3 on page 38).
Verify pinout availability in Table 4: Pin description on page 32.
Bit 0:
Sel_P10 Port1 [0] I/O multiplexing scheme:
0: Port1 [0] is interconnected to GPIO1 [0] signal
1: Port1 [0] is interconnected to PWM [0] signal
Bit 1:
Sel_P11 Port1 [1] I/O multiplexing scheme:
0: Port1 [1] is interconnected to GPIO1 [1] signal
1: Port1 [1] is interconnected to PWM [1] signal
Bit 2:
Sel_P12 Port1 [2] I/O multiplexing scheme:
0: Port1 [2] is interconnected to GPIO1 [2] signal
1: Port1 [2] is interconnected to PWM [2] signal
Bit 3:
Sel_P13 Port1 [3] I/O multiplexing scheme:
0: Port1 [3] is interconnected to GPIO1 [3] signal
1: Port1 [3] is interconnected to PWM [3] signal
Bit 4:
Sel_P14 Port1 [4] I/O multiplexing scheme:
0: Port1 [4] is interconnected to GPIO1 [4] signal
1: Port1 [4] is interconnected to PWM [4] signal
Bit 5:
Sel_P15 Port1 [5] I/O multiplexing scheme:
0: Port1 [5] is interconnected to GPIO1 [5] signal
1: Port1 [5] is interconnected to PWM [5] signal
42/126
DocID027870 Rev 1