SPEAR-09-H022_06 Datasheet, PDF (40/71 Pages) STMicroelectronics – SPEAr Head200 ARM 926, 200K customizable eASIC gates, large IP portfolio SoC

DMA controller block
11 DMA controller block
SPEAR-09-H022
SPEAr Head200 has 2 DMA Controllers used to transfer data between aASIC MacroCell
and memory.
A DMA Controller can service up to 4 data streams at one time; a data transfer consists of a
sequence of a DMA data packet transfers. There are two types of a data packet transfer
● one is from the source to the DMA Controller
● one other is from DMA Controller to the destination.
Each DMA Controller has an AHB Master interface to transfer data between DMA Controller
and either a source or a destination, and has an APB Slave interface used to program its
registers.
11.1
Functional description
Figure 7. DMA block diagram
As a DMA requests are received, the Request Logic will arbiter between them and set the
channel request signal. When a channel request is asserted, the State Machine starts a
data transfer: first a data packet is transferred from a source to the DMA channel and then
from the FIFO to the destination.
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