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STL3N10F7 Datasheet, PDF (4/13 Pages) STMicroelectronics – N-channel enhancement mode
Electrical characteristics
2
Electrical characteristics
STL3N10F7
(TCASE=25 °C unless otherwise specified)
Symbol
Parameter
Table 4. On/off states
Test conditions
Min. Typ. Max. Unit
Drain-source breakdown
V(BR)DSS voltage, VGS= 0
ID = 250 μA
100
V
Zero gate voltage drain
IDSS current (VGS = 0)
VDS = 100 V
VDS = 100 V, TC= 125 °C
1 μA
100 μA
Gate body leakage current
IGSS
(VDS = 0)
VGS = ± 20 V
±100 nA
VGS(th) Gate threshold voltage
VDS= VGS, ID = 250 μA
2.5
4.5 V
Static drain-source on-
RDS(on)
resistance
VGS= 10 V, ID= 2 A
0.062 0.07 Ω
Symbol
Parameter
Ciss
Coss
Crss
Qg
Qgs
Qgd
Input capacitance
Output capacitance
Reverse transfer
capacitance
Total gate charge
Gate-source charge
Gate-drain charge
Table 5. Dynamic
Test conditions
VDS =25 V, f=1 MHz,
VGS=0
VDD=50 V, ID = 4 A
VGS =10 V
(see Figure 14)
Min. Typ. Max. Unit
- 408 -
pF
- 112 -
pF
- 10
-
pF
- 7.8
-
nC
-
3
-
nC
- 1.7
-
nC
Symbol
Parameter
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Table 6. Switching times
Test conditions
VDD=50 V, ID= 2 A,
RG=4.7 Ω, VGS= 10 V
(see Figure 13)
Min. Typ. Max. Unit
- 6.3
-
ns
-
3
-
ns
- 11
-
ns
-
4
-
ns
4/13
DocID025948 Rev 2