STEF05 Datasheet, PDF (4/20 Pages) STMicroelectronics – Electronic fuse for 5 V line

Pin configuration
2
Pin configuration
STEF05
Figure 2. Pin configuration (top view)
Source
Source
Source
Source
Source
GND
dv/dt
V_CC
En/fault
I-Limit
N/C
AM09867v1
Table 2. Pin description
Pin n° Symbol
Note
1 to 5
6
7
8
9
10
11
V_OUT/Source
Connected to the source of the internal power MOSFET and to the output terminal of the
fuse
NC
Not connected
I-Limit
A resistor between this pin and the Source pin sets the overload and short-circuit current
limit levels.
En/Fault
The Enable/Fault pin is a tri-state, bi-directional interface. During normal operation the pin
must be left floating, or it can be used to disable the output of the device by pulling it to
ground using an open drain or open collector device.
If a thermal fault occurs, the voltage on this pin goes into an intermediate state to signal a
monitor circuit that the device is in thermal shutdown. It can be connected to another
device of this family to cause a simultaneous shutdown during thermal events.
dv/dt
The internal dv/dt circuit controls the slew rate of the output voltage at turn-on. The
internal capacitor allows a ramp-up time of around 1 ms. An external capacitor can be
added to this pin to increase the ramp time. If an additional capacitor is not required, this
pin should be left open.
GND
Ground pin
V_CC
Exposed pad. Positive input voltage must be connected to V_CC.
4/20
Doc ID 019055 Rev 4