STEF033 Datasheet, PDF (4/25 Pages) STMicroelectronics – Electronic fuse for 3.3 V line

Pin configuration
2
Pin configuration
Figure 2. Pin configuration (top view)
STEF033
Table 1. Pin description
Pin n°
(DFN)
Pin n°
(Flip Chip)
Symbol
Note
1,2,3,4,5
C1,C2,C3
V_OUT/Source
Connected to the source of the internal power MOSFET and to the
output terminal of the fuse
6
N.C.
I-lim - A resistor between these two pins sets the overload and short-circuit
current limit levels. On the Flip Chip the resistor must be connected
7
A1
I-lim + _{between the I-Lim+ and Source pins}
The Enable/Fault pin is a tri-state, bi-directional interface. During normal
operation the pin must be left floating, or it can be used to disable the
output of the device by pulling it to ground using an open drain or open
8
A2
En/Fault collector device. If a thermal fault occurs, the voltage on this pin goes
into an intermediate state to signal a monitor circuit that the device is in
thermal shutdown. It can be connected to another device of this family to
cause a simultaneous shutdown during thermal events.
9
N.C.
10
Exposed
pad
A3
B1,B2,B3
dv/dt
GND
V_CC
The internal dv/dt circuit controls the slew rate of the output voltage at
turn-on. The internal capacitor allows a ramp-up time of around 1.4 ms.
An external capacitor can be added to this pin to increase the ramp time.
If an additional capacitor is not required, this pin should be left open.
This feature is not available on the Flip Chip version.
Ground pin
Exposed pad. Positive input voltage must be connected to V_CC.
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