STD8N60DM2 Datasheet, PDF (4/15 Pages) STMicroelectronics – N-channel 600 V, 550 m(ohm) typ., 8 A MDmesh DM2 Power MOSFET in a DPAK package

Electrical characteristics
STD8N60DM2
2
Electrical characteristics
(Tcase = 25 °C unless otherwise specified)
Table 5: Static
Symbol
Parameter
Test conditions
V(BR)DSS
Drain-source breakdown
voltage
VGS = 0 V, ID = 1 mA
IDSS
Zero gate voltage drain
current
IGSS
Gate-body leakage
current
VGS = 0 V, VDS = 600 V
VGS = 0 V, VDS = 600 V,
Tcase = 125 °C⁽¹⁾
VDS = 0 V, VGS = ±25 V
VGS(th)
RDS(on)
Gate threshold voltage
Static drain-source on-
resistance
VDS = VGS, ID = 250 µA
VGS = 10 V, ID = 4 A
Min. Typ. Max. Unit
600
V
1
µA
100
±5 µA
3
4
5
V
550 600 mΩ
Notes:
(1)_{Defined by design, not subject to production test.}
Symbol
Ciss
Coss
Crss
Coss eq.⁽¹⁾
RG
Qg
Qgs
Qgd
Parameter
Input capacitance
Output capacitance
Reverse transfer
capacitance
Equivalent output
capacitance
Intrinsic gate resistance
Total gate charge
Gate-source charge
Gate-drain charge
Table 6: Dynamic
Test conditions
VDS = 100 V, f = 1 MHz,
VGS = 0 V
VDS = 0 to 480 V, VGS = 0 V
f = 1 MHz, ID = 0 A
VDD = 480 V, ID = 8 A,
VGS = 10 V (see Figure 15:
"Test circuit for gate charge
behavior")
Min. Typ. Max. Unit
- 449 -
-
24
-
pF
- 0.89 -
-
42
-
pF
- 6.5 -
Ω
- 13.5 -
-
3
- nC
- 7.7 -
Notes:
(1) _{Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS}
increases from 0 to 80% VDSS.
Symbol
Parameter
td(on)
tr
td(off)
Turn-on delay time
Rise time
Turn-off delay time
tf
Fall time
Table 7: Switching times
Test conditions
VDD = 300 V, ID = 4 A
RG = 4.7 Ω, VGS = 10 V (see
Figure 14: "Test circuit for
resistive load switching times"
and Figure 19: "Switching time
waveform")
Min. Typ. Max. Unit
-
10
-
-
6
-
- 25.4 -
ns
- 9.5 -
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