STM8S005C6 Datasheet, PDF (39/97 Pages) STMicroelectronics – Extended instruction set

STM8S005C6 STM8S005K6
Option bytes
Option byte no.
OPT0
OPT1
OPT2
OPT3
OPT4
Table 12. Option byte description
Description
ROP[7:0] Memory readout protection (ROP)
0xAA: Enable readout protection (write access via SWIM protocol) 
Note: Refer to the family reference manual (RM0016) section on
Flash/EEPROM memory readout protection for details.
UBC[7:0] User boot code area
0x00: no UBC, no write-protection
0x01: Pages 0 to 1 defined as UBC, memory write-protected
0x02: Pages 0 to 3 defined as UBC, memory write-protected
0x03: Pages 0 to 4 defined as UBC, memory write-protected
...
0xFE: Pages 0 to 255 defined as UBC, memory write-protected
0xFF: Reserved
Note: Refer to the family reference manual (RM0016) section on
Flash/EEPROM write protection for more details.
AFR[7:0]
Refer to Table 13: Description of alternate function remapping bits [7:0] of
OPT2
HSITRIM: high-speed internal clock trimming register size
0: 3-bit trimming supported in CLK_HSITRIMR register
1: 4-bit trimming supported in CLK_HSITRIMR register
LSI_EN: Low speed internal clock enable
0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
IWDG_HW: Independent watchdog
0: IWDG Independent watchdog activated by software
1: IWDG Independent watchdog activated by hardware
WWDG_HW: Window watchdog activation
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
WWDG_HALT: Window watchdog reset on halt
0: No reset generated on halt if WWDG active
1: Reset generated on halt if WWDG active
EXTCLK: External clock selection
0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
CKAWUSEL: Auto wakeup unit/clock
0: LSI clock source selected for AWU
1: HSE clock with prescaler selected as clock source for for AWU
PRSC[1:0] AWU clock prescaler
0x: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
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