M45PE80_06 Datasheet, PDF (38/47 Pages) STMicroelectronics – 8 Mbit, low voltage, Page-Erasable Serial Flash memory with byte alterability and a 50 MHz SPI bus interface

DC and AC parameters
M45PE80
Table 14.
AC characteristics (50 MHz operation)⁽¹⁾
50 MHz preliminary data for T9HX technology⁽²⁾
Test conditions specified in Table 8 and Table 9
Symbol Alt.
Parameter
Min.
Typ.
Max. Unit
Clock frequency for the following instructions:
f_C
f_C FAST_READ, PW, PP, PE, SE, DP, RDP,
D.C.
WREN, WRDI, RDSR, RDID
f_R
Clock frequency for READ instructions
D.C.
t_CH(3) t_CLH Clock High time
9
t_CL(3) t_CLL Clock Low time
9
Clock slew rate⁽⁴⁾ (peak to peak)
0.1
t_SLCH t_CSS S active setup time (relative to C)
5
t_CHSL
S not active hold time (relative to C)
5
t_DVCH t_DSU Data in setup time
2
t_CHDX t_DH Data in hold time
5
t_CHSH
S active hold time (relative to C)
5
t_SHCH
S not active setup time (relative to C)
5
t_SHSL t_CSH S deselect time
100
t_SHQZ(4) t_DIS Output disable time
t_CLQV
t_V Clock Low to Output Valid
t_CLQX t_HO Output hold time
0
t_WHSL
Write Protect setup time
50
t_SHWL
Write Protect hold time
100
t_DP(4)
S to Deep Power-down
t_RDP(4)
S High to Standby mode
t_RLRH(4) t_RST Reset pulse width
t_RHSL t_REC Reset recovery time
t_SHRH
Chip should have been deselected before
Reset is de-asserted
t_PW(5)
Page Write cycle time (256 bytes)
t_PP(5)
Page Program cycle time (256 bytes)
Page Program cycle time (n bytes)
11
0.8
int(n/8) × 0.025
50 MHz
33 MHz
ns
ns
V/ns
ns
ns
ns
ns
ns
ns
ns
8
ns
8
ns
ns
ns
ns
3
µs
30
µs
10
µs
3
µs
10
ns
23 ms
3
ms
t_PE
Page Erase cycle time
10
20 ms
t_SE
Sector Erase cycle time
1
5
s
1. Preliminary data.
2. Delivery of parts in T9HX process to start from June 2007.
3. t_CH + t_CL must be greater than or equal to 1/ f_C
4. Value guaranteed by characterization, not 100% tested in production.
5. n = number of bytes to program. int(A) corresponds to the upper integer part of A. Examples: int(1/8) = 1, int(16/8) = 2,
int(17/8) = 3.
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