M45PE80_06 Datasheet, PDF (31/47 Pages) STMicroelectronics – 8 Mbit, low voltage, Page-Erasable Serial Flash memory with byte alterability and a 50 MHz SPI bus interface

M45PE80
7
Power-up and Power-down
Power-up and Power-down
At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on V_CC) until V_CC reaches the correct value:
● V_CC(min) at Power-up, and then for a further delay of t_VSL
● V_SS at Power-down
A safe configuration is provided in Section 3: SPI modes.
To avoid data corruption and inadvertent write operations during power up, a Power On
Reset (POR) circuit is included. The logic inside the device is held reset while V_CC is less
than the POR threshold value, V_WI – all operations are disabled, and the device does not
respond to any instruction.
Moreover, the device ignores all Write Enable (WREN), Page Write (PW), Page Program
(PP), Page Erase (PE) and Sector Erase (SE) instructions until a time delay of t_PUW has
elapsed after the moment that V_CC rises above the V_WI threshold. However, the correct
operation of the device is not guaranteed if, by this time, V_CC is still below V_CC(min). No
Write, Program or Erase instructions should be sent until the later of:
● t_PUW after V_CC passed the V_WI threshold
● t_VSL after V_CC passed the V_CC(min) level
These values are specified in Table 6.
If the delay, t_VSL, has elapsed, after V_CC has risen above V_CC(min), the device can be
selected for READ instructions even if the t_PUW delay is not yet fully elapsed.
As an extra protection, the Reset (Reset) signal could be driven Low for the whole duration
of the Power-up and Power-down phases.
At Power-up, the device is in the following state:
● The device is in the Standby mode (not the Deep Power-down mode).
● The Write Enable Latch (WEL) bit is reset.
● The Write In Progress (WIP) bit is reset.
Normal precautions must be taken for supply rail decoupling, to stabilize the V_CC feed. Each
device in a system should have the V_CC rail decoupled by a suitable capacitor close to the
package pins. (Generally, this capacitor is of the order of 100 nF).
At Power-down, when V_CC drops from the operating voltage, to below the POR threshold
value, V_WI, all operations are disabled and the device does not respond to any instruction.
(The designer needs to be aware that if a Power-down occurs while a Write, Program or
Erase cycle is in progress, some data corruption can result.)
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