ST6373 Datasheet, PDF (37/64 Pages) STMicroelectronics – 8-BIT ROM/OTP/EPROM MCUs FOR DIGITALLY CONTROLLED MULTISYNC/MULTISTANDARD MONITORS

ST6373
TIMERS (Cont’d)
4.2.2 Timer Status Control Registers (TSCR)
Timers 1 and 2
Address: D4h (Timer 1), DCh (Timer 2) -
Read/Write
Reset Value: 00h
7
0
TMZ ETI D5 D4 PSI PS2 PS1 PS0
TMZ. Low-to-high transition indicates that the tim-
er count register has decremented to zero. This bit
must be cleared by user software before to start
with a new count.
ETI. This bit, when set, enables the timer interrupt
(vector #3 for Timer 1, vector #2 for Timer 2 re-
quest). If ETI=0 the timer interrupt is disabled. If
ETI= 1 and TMZ= 1 an interrupt request is gener-
ated.
D5. This is the timers enable bit D5. It must be
cleared to 0 together with a set to 1 of bit D4 to en-
able Timer 1 and Timer 2 functions. It is not imple-
mented on registers TSCR2.
D4. This is the timers enable bit D4. This bit must
be set to 1 together with a clear to 0 of bit D5 to en-
able all Timers (Timer 1 and 2) functions. It is not
implemented on registers TSCR2.
D5
D4
Timers
0
0
Disabled
0
1
Enabled
1
X
Reserved
PSI. Used to initialize the prescaler and inhibit its
counting while PSI = 0 the prescaler is set to 7Fh
and the counter is inhibited. When PSI = 1 the
prescaler is enabled to count downwards. As long
as PSI= 0 both counter and prescaler are not run-
ning.
PS2-PS0. These bits select the division ratio of the
prescaler register. (see Table 11)
The TSCR1 and TSCR2 registers are cleared on
reset. The correct D4-D5 combination must be
written in TSCR1 by user’s software to enable the
operation of Timer 1 and 2.
Table 11. Prescaler Division Factors
PS2
PS1
PS0
Divided By
0
0
0
1
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
4.2.3 Timer Counter Registers (TCR)
Timer Counter 1 and 2
Address: D3h (Timer Counter 1), DBh (Timer
Counter 2) - Read/Write
Reset Value: FFh
7
0
D7 D6 D5 D4 D3 D2 D1 D0
Bit 7-0 = D7-D0: Counter Bits.
4.2.4 Timer Prescaler Registers (PSCR)
Timer Prescalers 1 and 2
Address: D2h (Timer Prescaler 1), DAh (Timer
Prescaler 2) - Read/Write
Reset Value: 7Fh
7
0
D7 D6 D5 D4 D3 D2 D1 D0
Bit 7 = D7: Always read as ”0”.
Bit 6-0 = D6-D0: Prescaler Bits.
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