ST72311R Datasheet, PDF (36/164 Pages) STMicroelectronics – 8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC, 16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES

ST72311R, ST72511R, ST72512R, ST72532R
POWER SAVING MODES (Cont’d)
7.4 ACTIVE-HALT AND HALT MODES
ACTIVE-HALT and HALT modes are the two low-
est power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruc-
tion. The decision to enter either in ACTIVE-HALT
or HALT mode is given by the MCC/RTC interrupt
enable flag (OIE bit in MCCSR register).
MCCSR Power Saving Mode entered when HALT
OIE bit
instruction is executed
0 HALT mode
1 ACTIVE-HALT mode
7.4.1 ACTIVE-HALT MODE
ACTIVE-HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ in-
struction when the OIE bit of the Main Clock Con-
troller Status register (MCCSR) is set (see Section
10.2 on page 52 for more details on the MCCSR
register).
The MCU can exit ACTIVE-HALT mode on recep-
tion of either an MCC/RTC interrupt, a specific in-
terrupt (see Table 7, “Interrupt Mapping,” on
page 32) or a RESET. When exiting ACTIVE-
HALT mode by means of a RESET or an interrupt,
a 4096 CPU cycle delay occurs. After the start up
delay, the CPU resumes operation by servicing
the interrupt or by fetching the reset vector which
woke it up (see Figure 22).
When entering ACTIVE-HALT mode, the I[1:0] bits
in the CC register are forced to ‘10’ to enable inter-
rupts. Therefore, if an interrupt is pending, the
MCU wakes up immediately.
In ACTIVE-HALT mode, only the main oscillator
and its associated counter (MCC/RTC) are run-
ning to keep a wake-up time base. All other periph-
erals are not clocked except those which get their
clock supply from another clock generator (such
as external or auxiliary oscillator).
The safeguard against staying locked in ACTIVE-
HALT mode is provided by the oscillator interrupt.
Note: As soon as the interrupt capability of one of
the oscillators is selected (MCCSR.OIE bit set),
entering ACTIVE-HALT mode while the Watchdog
is active does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.
Figure 21. ACTIVE-HALT Timing Overview
ACTIVE _{4096 CPU CYCLE}
RUN HALT
DELAY
RUN
HALT
INSTRUCTION
[MCCSR.OIE=1]
RESET
OR
INTERRUPT
FET CH
VECTOR
Figure 22. ACTIVE-HALT Mode Flow-chart
HALT INSTRUCTION
(MC CSR.OI E=1)
OSCILLATOR ON
PERIPHERALS ¹⁾ OFF
CPU
OFF
I[1:0] BITS
10
N
RESET
N
Y
INTERRUPT ²⁾
Y
OSCILLATOR ON
PERIPHERALS OFF
CPU
ON
I[1:0] BITS
XX ³⁾
4096 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
ON
ON
XX ³⁾
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
1. Peripheral clocked with an external clock source
can still be active.
2. Only the MCC/RTC interrupt and some specific
interrupts can exit the MCU from ACTIVE-HALT
mode (such as external interrupt). Refer to
Table 7, “Interrupt Mapping,” on page 32 for more
details.
3. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and restored when the CC
register is popped.
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