ST72311R Datasheet, PDF (136/164 Pages) STMicroelectronics – 8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC, 16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES

ST72311R, ST72511R, ST72512R, ST72532R
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
12.4.2 WAIT and SLOW WAIT Modes
Symbol
Parameter
Supply current in WAIT mode ³⁾
(see Figure 71)
Supply current in SLOW WAIT mode ⁴⁾
(see Figure 72)
I_DD
Supply current in WAIT mode ³⁾
(see Figure 71)
Supply current in SLOW WAIT mode ⁴⁾
(see Figure 72)
Conditions
f_OSC=1MHz, f_CPU=500kHz
f_OSC=4MHz, f_CPU=2MHz
f_OSC=16MHz, f_CPU=8MHz
f_OSC=1MHz, f_CPU=31.25kHz
f_OSC=4MHz, f_CPU=125kHz
f_OSC=16MHz, f_CPU=500kHz
f_OSC=1MHz, f_CPU=500kHz
f_OSC=4MHz, f_CPU=2MHz
f_OSC=16MHz, f_CPU=8MHz
f_OSC=1MHz, f_CPU=31.25kHz
f_OSC=4MHz, f_CPU=125kHz
f_OSC=16MHz, f_CPU=500kHz
Typ ¹⁾ Max ²⁾ Unit
1.25
2
3.2
5
5.2
9
0.2 0.35
0.6
1
1.2
2
mA
0.7
1
1.6
2.6
2.7
4.5
0.1 0.15
0.3
0.5
0.6
1
Figure 71. Typical I_DD in WAIT vs. f_CPU
Figure 72. Typical I_DD in SLOW-WAIT vs. f_CPU
IDD [mA]
7
8MHz 2MHz 500kHz
6
IDD [mA]
1.5
500kHz 125kHz 31.25kHz
5
1
4
3
0.5
2
1
0
3
3.5
4
4.5
5
5.5
VDD [V]
0
3
3.5
4
4.5
VDD [V]
5
5.5
Notes:
1. Typical data are based on T_A=25°C, V_DD=5V (4.5V≤V_DD≤5.5V range) and V_DD=3.3V (3V≤V_DD≤3.6V range).
2. Data based on characterization results, tested in production at V_DD max. and f_CPU max.
3. All I/O pins in input mode with a static value at V_DD or V_SS (no load), all peripherals switched off; clock input (OSC1)
driven by external square wave, LVD disabled.
4. SLOW-WAIT mode selected with f_CPU based on f_OSC divided by 32. All I/O pins in input mode with a static value at
V_DD or V_SS (no load), all peripherals switched off; clock input (OSC1) driven by external square wave, LVD disabled.
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