SPC56EL60X Datasheet, PDF (36/165 Pages) STMicroelectronics – Dual issue five-stage pipeline core

Package pinouts and signal descriptions
SPC56ELx, SPC564Lx
Figure 4. SPC56ELx/SPC564Lx LFBGA257 pinout (top view)
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A ^{VSS_HV_I VSS_HV_I VDD_HV_}
O
O
IO
H[2]
H[0]
G[14]
D[3]
C[15] ^VDD_HV_ A[12]
IO
B ^{VSS_HV_I VSS_HV_I}
B[6]
A[14]
F[3]
A[9]
D[4]
D[0] ^VSS_HV_I H[12]
O
O
O
C
V_{DD_HV_}
IO
NC⁽¹⁾
V_{SS_HV_I} FCCU_F
O
[1]
D[2]
A[13] ^{VDD_HV_ VDD_HV_}
I[0]
REG_2
REG_2
JCOMP
D
F[5]
F[4]
A[15]
C[6]
V_{SS_LV_} V_{DD_LV_}
F[0]
V_{DD_HV_} V_{SS_HV_I}
NC
COR
COR
IO
O
11
H[10]
E[15]
H[11]
A[11]
E ^MDO0
F[6]
D[1]
NMI
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H[14]
E[14]
I[1]
E[13]
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14
15
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17
A[10]
B[2]
C[10]
V_{SS_HV_I} V_{SS_HV_I}
O
O
B[3]
F[13]
B[0]
V_{DD_HV_} V_{SS_HV_I}
IO
O
F[14]
B[1] ^VSS_HV_I A[4]
O
F[12]
F[15]
V_{DD_HV_}
IO
V_PP
_TEST
D[14]
G[3]
NC
C[14]
G[2]
I[3]
F
H[1]
G[12]
A[7]
A[8]
G
H[3] ^VDD_HV_ C[5]
A[6]
IO
H
G[13] ^VSS_HV_I C[4]
A[5]
O
J
F[7]
G[15] ^{VDD_HV_ VDD_HV_}
REG_0
REG_0
V_{DD_LV_} V_{DD_LV_} V_{DD_LV_} V_{DD_LV_} V_{DD_LV_} V_{DD_LV_} V_{DD_LV_}
COR
COR
COR
COR
COR
COR
COR
V_{DD_LV_} V_{SS_LV_} V_{SS_LV_} V_{SS_LV_} V_{SS_LV_} V_{SS_LV_} V_{DD_LV_}
COR
COR
COR
COR
COR
COR
COR
V_{DD_LV} V_{SS_LV} V_{SS_LV} V_{SS_LV} V_{SS_LV} V_{SS_LV} V_{DD_LV}
V_{DD_LV} V_{SS_LV} V_{SS_LV} V_{SS_LV} V_{SS_LV} V_{SS_LV} V_{DD_LV}
NC
C[13]
I[2]
G[4]
D[12] H[13]
H[9]
G[6]
V_{SS_LV}
V_{DD_HV_} V_{DD_HV_}
REG_1
FLA
V_{DD_LV}
V_{DD_HV_} V_{SS_HV_}
REG_1
FLA
H[6]
H[15]
K
F[9]
F[8]
C[7]
V_{DD_LV} V_{SS_LV} V_{SS_LV} V_{SS_LV} V_{SS_LV} V_{SS_LV} V_{DD_LV}
NC
H[8]
H[7]
A[3]
L
F[10]
F[11]
D[9]
NC
V_{DD_LV} V_{SS_LV} V_{SS_LV} V_{SS_LV} V_{SS_LV} V_{SS_LV} V_{DD_LV}
NC
TCK
H[4]
B[4]
M ^{VDD_HV_ VDD_HV_}
D[8]
NC
OSC
IO
V_{DD_LV} V_{DD_LV} V_{DD_LV} V_{DD_LV} V_{DD_LV} V_{DD_LV} V_{DD_LV}
C[11]
B[5]
TMS
H[5]
N
XTAL ^VSS_HV_I D[5]
V_{SS_LV_}
O
PLL
NC
C[12]
A[2]
G[5]
P VSS_HV_ RESET
OSC
D[6]
V_{DD_LV_} V_{DD_LV_} V_{SS_LV_}
PLL
COR
COR
B[8]
NC
V_{SS_HV_I} V_{DD_HV_}
B[14]
V_{DD_LV_} V_{SS_LV_} V_{DD_HV_}
G[10]
O
IO
COR
COR
IO
G[8]
G[7]
R
EXTAL
FCCU V_{SS_HV_I}
_F[0]
O
D[7]
B[7]
E[6]
V_{DD_HV_}
ADR0
B[10]
V_{DD_HV_}
ADR1
B[13]
B[15]
C[0]
BCTRL
A[1] ^VSS_HV_I D[11]
O
G[9]
T ^{VSS_HV_I VDD_HV_}
NC
O
IO
C[1]
E[5]
E[7]
V_{SS_HV_ B[11]} V_{SS_HV_}
E[9]
E[10] E[12]
E[0]
ADR0
ADR1
A[0]
D[10]
V_{DD_HV_} V_{SS_HV_I}
IO
O
U ^{VSS_HV_I VSS_HV_I}
NC
O
O
E[4]
C[2]
E[2]
B[9]
B[12] ^{VDD_HV_ VSS_HV_} E[11]
NC
ADV
ADV
NC
V_{DD_HV_ G[11]} V_{SS_HV_I} V_{SS_HV_I}
PMU
O
O
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1. NC = Not connected (the pin is physically not connected to anything on the device).
Table 3, Table 4, and Table 5 provide the pin function summaries for the 100-pin, 144-pin,
and 257-pin packages, respectively, listing all the signals multiplexed to each pin.
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