TDA7529 Datasheet, PDF (35/60 Pages) STMicroelectronics – RF front-end for AM/FM DSP car-radio with IF sampling

TDA7529
6
Registers description
Registers description
Figure 16. Registers description
No name
0 Short reg
1 ADCctrl
2 GPIOval
3 AGCmixCtrl
4 Misc1
5 DivR
6 IFAGC_SH
7 FMAGC
8 FM_AM_Vthr
9 MIXalign1
10 MIXalign2
11 PLLctrl
12 PLLctrl2
13 PLLtest
14 Misc2
15 WAIT_LOCK
16 AGCtc_A
17 AMAGC_A
18 GPIOm_A
19 IFCTRL_A
20
21 DivN_A1
22 DivN_A2
23 DivN_A3
24 DivV_A
25 CPcur_A
26 DAC1_A
27 DAC2_A
28 PLL_DAC_A
29 Misc4_A
30
31
32 AGCtc_B
33 AMAGC_B
34 GPIOm_B
35 IFCTRL_B
36 AMFilt_B
37 DivN_B1
38 DivN_B2
39 DivN_B3
40 DivV_B
41 CPcur_B
42 DAC1_B
43 DAC2_B
44 PLL_DAC_B
45 Misc4_B
46
47
48 READ_Status
49 READ_ADC
Power
r/w
MSB (7)
6
5
4
3
2
1
LSB (0)
on
r/w
x
x
ShAGC
r/w
ADCclk
ADCs2
ADCs1
r/w GPO8_AMAGCv GPO7_FMAGCv GPIO6_MISO
ShPLL
ADCs0
GPIO5_Aout
ADCstart
GPO4_AMcas
ADCen
RCenable
CP_curr_switch
GPIOen
ADCautomode
GPIO2io
PWR
Temp_pwr
GPIO1io
default
00h
00h
00h
r/w IFin1_AM_FM
KeyAGCen
FMAGCpwr
AMAGCpwr
MixinFMAM
BalunoutIMP
Mixout1
Mixout2
00h
r/w WAIT60ms(4) WAIT60ms(3) WAIT60ms(2) WAIT60ms(1) WAIT60ms(0)
disvcc
PLLtest
AMAGC_Isink
00h
r/w
divr7
divr6
divr5
divr4
divr3
divr2
divr1
divr0
00h
r/w IFAGC_FM_AM
IFAGCthr2
IFAGCthr1
IFAGCthr0
GPIO5 output
IFsection_pwr
00h
r/w
FMthr3
FMthr2
FMthr1
FMthr0
FMAGCmodeC1 FMAGCmodeC0 FMAGCmodeV1 FMAGCmodeV0
00h
r/w
AMAGCfat
AFH_MUX
Vthr5
Vthr4
Vthr3
Vthr2
Vthr1
Vthr0
00h
r/w
IFAMP_Ictrl2
IFAMP_Ictrl1
r/w
IMRph3
IMRph2
IredH
IMRph1
IredL
IMRph0
Casc_ctrl
IMRG3
IMRF2
IMRG2
IMRF1
IMRG1
IMRF0
00h
IMRG0
00h
r/w
DZ4
r/w
FUNC
DZ3
MODE2
DZ2
MODE1
DZ1
MODE0
CPcur_800u
DS4
SWfref
DS3
divRen
DS2
PLLpwr
00h
DS1
00h
r/w
POL
PFD_D1
PFD_D0
PLLT4
PLLT3
PLLT2
PLLT1
PLLT0
00h
r/w
IFAGCin4ctrl
EnSMOOTH
reg48sel
IFAMP_Ictrl0
RCfreq_1
RCfreq_0
VCOMag1
VCOMag0
00h
r/w WAIT LOCK(4) WAIT LOCK(3) WAIT LOCK(2) WAIT LOCK(1) WAIT LOCK(0)
DIVVtest
VCOext
LOCK_bit
00h
r/w
IFAGCtcAM
IFAGCtcFM
AMtc1
AMtc0
FMtc3
FMtc2
FMtc1
FMtc0
00h
r/w
AMthr3
AMthr2
AMthr1
AMthr0
AMAGCmodeC1 AMAGCmodeC0 AMAGCmodeV1 AMAGCmodeV0
00h
r/w
GPO8hl
GPO7hl
GPIO6hl
GPIO5hl
GPO4hl
GPIO2hl
GPIO1hl
00h
r/w IFin0_Std_IBOC IFAmpgainA2 IFAmpgainA1 IFAmpgainA0
MixinFM
AMAGCinbuffer
RCtest
00h
r/w
WAIT1ms(5)
WAIT1ms(4)
WAIT1ms(3)
WAIT1ms(2)
WAIT1ms(1)
WAIT1ms(0)
00h
r/w
divnA20
divnA19
divnA18
divnA17
divnA16
divnA15
divnA14
divnA13
00h
r/w
divnA12
divnA11
divnA10
divnA9
divnA8
divnA7
divnA6
divnA5
00h
r/w
divnA4
divnA3
divnA2
divnA1
divnA0
00h
r/w
VCO1r
divVA6
divVA5
divVA4
divVA3
divVA2
divVA1
divVA0
00h
r/w
CPAh3
CPAh2
CPAh1
CPAh0
CPAl3
CPAl2
CPAl1
CPAl0
00h
r/w
DAC1A8
DAC1A6
DAC1A5
DAC1A4
DAC1A3
DAC1A2
DAC1A1
DAC1A1
00h
r/w
DAC2A8
DAC2A6
DAC2A5
DAC2A4
DAC2A3
DAC2A2
DAC2A1
DAC2A1
00h
r/w
IQselA
VCOsw
DAC2A0
DAC1A0
DAC2off
DAC1off
00h
r/w
WAIT2ms(5)
WAIT2ms(4)
WAIT2ms(3)
WAIT2ms(2)
WAIT2ms(1)
WAIT2ms(0)
MIN16
00h
r/w WAIT0.5ms(5) WAIT0.5ms(4) WAIT0.5ms(3) WAIT0.5ms(2) WAIT0.5ms(1) WAIT0.5ms(0)
AGCtest1
AGCtest0
00h
r/w
IF test
ADC test
ADCDAC5
ADCDAC4
ADCDAC3
ADCDAC2
ADCDAC1
ADCDAC0
00h
r/w
this byte is valid on the output if bit SHAGC is set to '1', otherwise byte Nr. 16 is valid on the output
00h
r/w
all bytes from 33 to 45 are valid on the output if SHPLL is set to '1', otherwise byte 17 to 29 are valid on the output
00h
r/w
00h
r/w
00h
r/w
00h
r/w
00h
r/w
00h
r/w
00h
r/w
00h
r/w
00h
r/w
00h
r/w
00h
r/w
00h
r/w
00h
00h
00h
r
lock
GPIO6r
GPIO5r
MaskMetal1
MaskMetal0
MaskSet1
MaskSet0
00h
r
ADCok
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
00h
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