AN3393 Datasheet, PDF (35/103 Pages) STMicroelectronics – This document is intended to provide information

AN3393
Register description
Table 54. SETT1 register structure
P_DET THR3_SA ABS
-
-
THR3_MA R_TAM SITR
P_DET
THR3_SA
ABS
THR3_MA
R_TAM
SITR
Table 55. SETT1 register description
SM1 peak detection bit. Default value: 0
0 = peak detection disabled, 1 = peak detection enabled
For more information about peak detection refer to Section 8.
Default value: 0
0 = no action, 1 = threshold 3 enabled for axis and sign mask reset (MASKB_1)
Default value: 0
0 = unsigned thresholds THRSx, 1 = signed thresholds THRSx
For more details refer to Section 7.2.
Default value: 0
0 = no action, 1 = threshold 3 enabled for axis and sign mask reset (MASKA_1)
Next condition validation flag. Default value: 0
0 = mask frozen on the axis that triggers the condition, 1 = standard mask always
evaluated.
For more details about the temporary axis mask refer to Section 7.3.
Default value:0
0 = no actions, 1 = STOP and CONT commands generate an interrupt and perform
output actions as OUTC command.
4.35
PR1 (5Ch)
Program and reset pointers for State Machine 1.
Table 56. PR1 register
RP3
RP2
RP1
RP0
PP3
PP2
PP1
PP0
RP3-RP0
PP3-PP0
Table 57. PR1 register description
SM1 reset pointer address
SM1 program pointer address
4.36
TC1 (5Dh-5Eh)
16-bit general timer counter for State Machine 1.
Table 58. TC1_L default values
0
0
0
0
0
0
0
0
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