TDA7540N Datasheet, PDF (34/76 Pages) STMicroelectronics – AM/FM car radio tuner IC with stereo decoder and intelligent selectivity system (ISS)

Functional description
TDA7540N
4.3.5
VQual = 0.8b (VNoise-0.8 V)+ a (V_REF1-VMpout).
The noise-signal is the PEAK-signal without additional influences (see noise blanker
description). The factor 'a' can be programmed from 0.6 to 1.05(QDC) and the factor b can
be programmed from 6dB to 15dB ( QNG). The output is a low impedance output able to
drive external circuitry as well as simply fed to an AD-converter for RDS applications.
AFS control and stereo decoder mute
The TDA7540N is supplied with several functionality to support AF-checks using the stereo
decoder. The additional pin (AFS) is implemented in order to speed up the stereo decoder
AF-functions compared to IIC controlling.
The block diagramm of AFS function is shown in Figure 17.
In order to separate the different functions of the AFS pin, two different logic thresholds are
implemented. Below the higher threshold voltage (2.4V) only the multipath-detector is
switched into small time constant (internal logical signal MPfast).
Below the lower threshold voltage (0.8V) the full AFS function is activated. The MPXIN pin is
switched into high impedance mode (internal signal AFSMute), which avoids any clicks
during the jump condition. If the stereo decoder is not muted, it is possible at the same time
to evaluate the noise- and multipath-content of the alternate frequency using the Quality
detector output.
Furthermore the AFS pin does also freeze the condition of pilot locking and magnitude
(internal signal PDhold). The Pdhold signal is defined by V_th1 or V_th2, dependent on the
PDH signal.
4.4
4.4.1
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PLL and IF counter section
PLL frequency synthesizer block
This part contains a frequency synthesizer and a loop filter for the radio tuning system. Only
one VCO is required to build a complete PLL system for FM world tuning and AM
upconversion (Figure 9). For auto search stop operation an IF counter system is available.
The PLL counter works in a two stages configuration. The first stage is a swallow counter
with a two modulus (32/33) precounter. The second stage is an 11-bit programmable
counter.
The circuit receives the scaling factors for the programmable counters and the values of the
reference frequencies via an I²C-Bus interface.The reference frequency is generated by an
adjustable internal (XTAL) oscillator followed by the reference divider. The main reference
and step-frequencies are free selectable (RC, PC).
Output signals of the phase detector are switching the programmable current sources. The
loop filter integrates their currents to a DC voltage.
The values of the current sources are programmable by 6 bits also received via the I²C Bus
(A, B, CURRH, LPF).
To minimize the noise induced by the digital part of the system, a special guard
configuration is implemented.
The loop gain can be set for different conditions by setting the current values of the
chargepump generator.