TDA7529_11 Datasheet, PDF (33/61 Pages) STMicroelectronics – RF front-end for AM/FM DSP car-radio with IF sampling

TDA7529
Table 25. Values of the programmable wait times
PARAMETER NAME
REGISTER
min.
T_plllock
T_0.5ms
Byte 15 bits<7:3>
Byte 30 bits<7:2>
default
maximum
min.
default
maximum
T_1ms
Byte 20 bits<7:2>
min.
default
maximum
min.
T_2ms
T_60ms
Byte 29 bits<7:2>
Byte 04 bits<7:3>
default
maximum
min.
default
maximum
Tuning state machine
VALUE
00000
00110
11111
000000
000101
111111
000000
001100
111111
000000
011000
111111
00000
10111
11111
TIME
20 us
1 ms
5 ms
70 us
0.5 ms
5 ms
10 us
1 ms
5 ms
50 us
2 ms
5 ms
1 ms
60 ms
80 ms
5.5
Register SWAP
Some of these modes contain one or two register "swap" operation(s). The changes within
the register structure during a swap operation depend on the operating mode of the chip.
If the chip is programmed in the "buffer/control" mode (chosen by setting byte 12 bit 7 = 1),
which is necessary to take advantage of the tuning state machine, it is suggested that the
microprocessor write data only in the normal register bank (bytes from 16 to 31), because
the state machine itself takes care of exchanging the content of the normal register bank
with that of the shadow bank (bytes from 32 to 47) during a swap. The normal registers are
intended to be written to by the radio microprocessor, whereas the registers that actually
control the device circuits are the shadow ones.
In any case it is suggested that the bits 5 and 4 of byte 0, that define which control bank is
actually used to drive the device circuits, should not be touched after setting them to 0 after
reset because they are automatically updated by the tuning state machine.
Doc ID 13311 Rev 4
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