STM8S103XX Datasheet, PDF (33/56 Pages) STMicroelectronics – Access line, STM8S 8-bit MCU, up to 32 Kbytes Flash, 10-bit ADC, timers, USART, SPI, I²C

STM8S103xx, STM8S105xx
Option bytes
Table 8. Option byte description (continued)
Option byte no.
Description
LSI_EN: Low speed internal clock enable
0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
OPT3
IWDG_HW: Independent watchdog
0: IWDG Independent watchdog activated by software
1: IWDG Independent watchdog activated by hardware
WWDG_HW: Window watchdog activation
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
WWDG_HALT: Window watchdog reset on halt
0: No reset generated on halt if WWDG active
1: Reset generated on halt if WWDG active
EXTCLK: External clock selection
0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
OPT4
CKAWUSEL: Auto wake-up unit/clock
0: LSI clock source selected for AWU
1: HSE clock with prescaler selected as clock source for for AWU
PRSC[1:0] AWU clock prescaler
00: Reserved
01: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
OPT5
HSECNT[7:0]: HSE crystal oscillator stabilization time
This configures the stabilisation time to 0, 16, 256, 4096 HSE cycles.
OPT6
OPT7
Reserved
Reserved
OPTBL
BL[7:0] Bootloader option byte
This option is checked by the boot ROM code after reset. Depending on
content of addresses 487Eh, 487Fh and 8000h (reset vector) the CPU
jumps to the bootloader or to the reset vector.
Refer to STM8S bootloader manual for more details.
33/56