STM32F205XX Datasheet, PDF (33/170 Pages) STMicroelectronics – USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

STM32F205xx, STM32F207xx
Description
2.2.30
2.2.31
2.2.32
suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock
that is generated by a PLL connected to the HSE oscillator. The major features are:
● Combined Rx and Tx FIFO size of 1024× 35 bits with dynamic FIFO sizing
● Supports the session request protocol (SRP) and host negotiation protocol (HNP)
● 6 bidirectional endpoints
● 12 host channels with periodic OUT support
● Internal FS OTG PHY support
● External FS OTG PHY support through an I²C connection
● External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is
connected to the microcontroller ULPI port through 12 signals. It can be clocked using
the 60 MHz output.
● Internal USB DMA
● HNP/SNP/IP inside (no need for any external resistor)
● For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
Audio PLL (PLLI2S)
The devices feature an additional dedicated PLL for audio I²S application. It allows to
achieve error-free I²S sampling clock accuracy without compromising on the CPU
performance, while using USB peripherals.
The PLLI2S configuration can be modified to manage an I²S sample rate change without
disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 kHz to 192 kHz.
In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S
flow with an external PLL (or Codec output).
Digital camera interface (DCMI)
The camera interface is not available in STM32F205xx devices.
STM32F207xx products embed a camera interface that can connect with camera modules
and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The
camera interface can sustain up to 27 Mbyte/s at 27 MHz or 48 Mbyte/s at 48 MHz. It
features:
● Programmable polarity for the input pixel clock and synchronization signals
● Parallel data communication can be 8-, 10-, 12- or 14-bit
● Supports 8-bit progressive video monochrome or raw Bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
● Supports continuous mode or snapshot (a single frame) mode
● Capability to automatically crop the image
True random number generator (RNG)
All STM32F2xxx products embed a true RNG that delivers 32-bit random numbers
produced by an integrated analog circuit.
Doc ID 15818 Rev 8
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