AN3981 Datasheet, PDF (33/54 Pages) STMicroelectronics – LED array drivers

AN3981
STP24DP05
4.8
Data flow management
The data are transferred from the shift register to each color group with a sequence defined
by the status of pins DF0 and DF1 and clarified in Figure 39.
Figure 39. Data flow management
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4.9
Gradual output delay
This feature is used to prevent high inrush current due to the simultaneous turning on of all
LEDs at the start of a video frame and so reducing the input capacitor value.
The gradual output delay can be activated by setting low the DG pin. A default delay of 30 ns
for each group (RGB) is implemented, as clarified by Figure 40.
Figure 40. Gradual output delay
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Doc ID 022217 Rev 1
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