AN3981 Datasheet, PDF (22/54 Pages) STMicroelectronics – LED array drivers

16-bit LED array drivers
AN3981
The error detection process can be divided into three phases:
1. Entering detection mode. From “normal mode” the device can enter “error mode”
through a logic key (Figure 23), which is a logic sequence of the OE ⁄ DM2 and LE/DM1
signals over five CLK cycles. After these five CLK cycles, the device is in “error
detection mode” and ready for sampling data on the SDI pin
2. Error detection. Once the device has entered “error detection mode”, an 8-bit string
should be loaded into the shift register through the SDI pin in order to set the outputs in
accordance with the diagnostic demands (only the outputs that are on are checked by
the error detection process). Therefore, if the user wants to check all the outputs, a
string with all “1” must be sent. After that the outputs are ready for the detection
process, which starts when OE ⁄ DM2 is set low. The device drives LEDs in order to
analyze if an open or short condition has occurred. The OE ⁄ DM2 must remain low for
at least 1 µs to complete the detection process. As shown in Figure 25, during the
detection process, at least three clock pulses are necessary: two pulses as soon as the
OE ⁄ DM2 OE – R is set low, one clock pulse before ending the detection process.
Once the OE ⁄ DM2 is set high, the error status code is available at the SDO pin. To
download the complete error string, at least 8 clock pulses are necessary
3. Resuming normal mode. The device quits detection mode and returns to normal mode
through an exit logic key (Figure 24), a logic sequence over five clock pulses.
Figure 23. Digital key for entering error
detection mode in 16-bit LED
drivers
Figure 24. Digital key for exiting error
detection mode in 16-bit LED
drivers





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For proper device operation, the entering sequence must be followed by a resuming
sequence as it is not possible to insert consecutive equal sequences.
Figure 25 shows an example of error detection where OUT15 and OUT0 are faulty, whereas
all other outputs are considered good.
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Doc ID 022217 Rev 1