STM32L486XX Datasheet, PDF (31/233 Pages) STMicroelectronics – Batch acquisition mode

STM32L486xx
Functional overview
3.10
Interconnect matrix
Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run
and sleep, Stop 0, Stop 1 and Stop 2 modes.
Table 6. STM32L486xx peripherals interconnect matrix
Interconnect source
Interconnect
destination
Interconnect action
TIMx
TIM16/TIM17
COMPx
ADCx
RTC
TIMx
ADCx
DACx
DFSDM1
DMA
COMPx
IRTIM
TIM1, 8
TIM2, 3
LPTIMERx
TIM1, 8
TIM16
LPTIMERx
All clocks sources (internal ^TIM2
and external)
TIM15, 16, 17
USB
TIM2
CSS
CPU (hard fault)
RAM (parity error)
Flash memory (ECC error) _TIM1,8
COMPx
TIM15,16,17
PVD
DFSDM1 (analog
watchdog, short circuit
detection)
Timers synchronization or chaining
YYYY - -
Conversion triggers
YYYY - -
Memory to memory transfer trigger
Comparator output blanking
Infrared interface output generation
YYYY - -
YYYY - -
YYYY - -
Timer input channel, trigger, break from
analog signals comparison
YYYY - -
Low-power timer triggered by analog
signals comparison
Y
Y
Y
Y
Y
Y
(1)
Timer triggered by analog watchdog
YYYY - -
Timer input channel from RTC events
YYYY - -
Low-power timer triggered by RTC alarms
or tampers
Y
Y
Y
Y
Y
Y
(1)
Clock source used as input channel for
RC measurement and trimming
YYYY - -
Timer triggered by USB SOF
YY - - - -
Timer break
YYYY - -
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