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M24C32-FDW6TP Datasheet, PDF (31/40 Pages) STMicroelectronics – 32-Kbit serial I²C bus EEPROM
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
DC and AC parameters
Table 19. 1 MHz AC characteristics
Symbol Alt.
Parameter(1)
Min.
Max.
Unit
fC
fSCL Clock frequency
0
1
MHz
tCHCL
tHIGH Clock pulse width high
260
-
ns
tCLCH
tXH1XH2
tXL1XL2
tQL1QL2(3)
tLOW
tR
tF
tF
Clock pulse width low
Input signal rise time
Input signal fall time
SDA (out) fall time
500
-
ns
(2)
(2)
ns
(2)
(2)
ns
20(4)
120
ns
tDXCX tSU:DAT Data in setup time
50
-
ns
tCLDX
tCLQX(5)
tCLQV(6)
tHD:DAT Data in hold time
tDH Data out hold time
tAA Clock low to next data valid (access time)
0
-
ns
100
-
ns
450
ns
tCHDL tSU:STA Start condition setup time
250
-
ns
tDLCL tHD:STA Start condition hold time
250
-
ns
tCHDH tSU:STO Stop condition setup time
250
-
ns
tDHDL
tBUF
Time between Stop condition and next Start
condition
500
-
ns
tWLDL(7)(3) tSU:WC WC set up time (before the Start condition)
0
tDHWH(8)(3) tHD:WC WC hold time (after the Stop condition)
1
tW
tWR Write time
-
-
µs
-
µs
5(9)
ms
tNS(3)
Pulse width ignored (input filter on SCL and
SDA)
-
80
ns
1. Only for M24C32 devices identified by the process letter K (devices qualified at 1 MHz).
2. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be less than 120 ns when fC < 1 MHz.
3. Characterized only, not tested in production.
4. With CL = 10 pF.
5. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or
0.7 VCC, assuming that the Rbus × Cbus time constant is within the values specified in Figure 12.
7. WC=0 set up time condition to enable the execution of a WRITE command.
8. WC=0 hold time condition to enable the execution of a WRITE command.
9. 10 ms for the M24C32-X, when VCC< 1.7 V.
Doc ID 4578 Rev 21
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