M24C04-DRE Datasheet, PDF (30/41 Pages) STMicroelectronics – 4-Kbit serial IC bus EEPROM - 105C operation

DC and AC parameters
M24C04-DRE
Table 11. 400 kHz AC characteristics
Symbol
Alt.
Parameter
Min.
Max. Unit
f_C
t_CHCL
t_CLCH
t_QL1QL2 ⁽¹⁾
t_XH1XH2
t_XL1XL2
t_DXCH
t_CLDX
t_CLQX ⁽⁴⁾
t_CLQV ⁽⁵⁾
t_CHDL
t_DLCL
t_CHDH
t_DHDL
t_WLDL(1)(6)
t_DHWH(1)(7)
t_W
t_NS ⁽¹⁾
f_SCL
t_HIGH
t_LOW
t_F
t_R
t_F
t_SU:DAT
t_HD:DAT
t_DH
t_AA
t_SU:STA
t_HD:STA
t_SU:STO
t_BUF
t_SU:WC
t_HD:WC
t_WR
-
Clock frequency
Clock pulse width high
Clock pulse width low
SDA (out) fall time ⁽²⁾
Input signal rise time
Input signal fall time
Data in set up time
Data in hold time
Data out hold time
Clock low to next data valid (access time)
Start condition setup time
Start condition hold time
Stop condition set up time
Time between Stop condition and next Start
condition
WC set up time (before the Start condition)
WC hold time (after the Stop condition)
Write time
Pulse width ignored (input filter on SCL and
SDA) - single glitch
-
600
1300
20
(3)
(3)
100
0
100
-
600
600
600
1300
0
1
-
-
400
kHz
-
ns
-
ns
120
ns
(3)
ns
(3)
ns
-
ns
-
ns
-
ns
900
ns
-
ns
-
ns
-
ns
-
ns
-
µs
-
µs
4
ms
80
ns
1. Characterized value, not tested in production.
2. With C_L = 10 pF.
3. There is no min. or max. values for the input signal rise and fall times. It is however
recommended by the I²C specification that the input signal rise and fall times be more than 20
ns and less than 300 ns when f_C < 400 kHz.
4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and
the falling or rising edge of SDA.
5.
F^0tC.i³g^LQVu^Vr^Ce^Cis1^o0^thr.^{e0.t7imVCeC(,fraosmsuthmeinfaglltihnagt}
edge
R_bus
of SCL) required by the SDA
× C_bus time constant is within
bus
the
line to
values
reach either
specified in
6. WC=0 set up time condition to enable the execution of a WRITE command.
7. WC=0 hold time condition to enable the execution of a WRITE command.
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