M24512-W_12 Datasheet, PDF (30/40 Pages) STMicroelectronics – 512-Kbit serial I²C bus EEPROM

DC and AC parameters
M24512-W M24512-R M24512-DR M24512-DF
Table 17. 1 MHz AC characteristics
Symbol Alt.
Parameter
Min.
Max.
Unit
f_C
f_SCL Clock frequency
0
t_CHCL
t_HIGH Clock pulse width high
300
t_CLCH
t_LOW Clock pulse width low
400
t_XH1XH2
t_R Input signal rise time
(1)
t_XL1XL2
t_F Input signal fall time
(1)
t_QL1QL2(2)
t_F SDA (out) fall time
-
t_DXCX t_SU:DAT Data in setup time
80
t_CLDX t_HD:DAT Data in hold time
0
t_CLQX(3)
t_DH Data out hold time
50
t_CLQV(4)
t_AA Clock low to next data valid (access time)
-
t_CHDL t_SU:STA Start condition setup time
250
t_DLCL t_HD:STA Start condition hold time
250
t_CHDH t_SU:STO Stop condition setup time
250
t_DHDL
t_BUF
Time between Stop condition and next Start
condition
500
t_WLDL(5)(2) t_SU:WC WC set up time (before the Start condition)
0
t_DHWH(6)(2) t_HD:WC WC hold time (after the Stop condition)
1
t_W
t_WR Write time
-
t_NS(2)
Pulse width ignored (input filter on SCL and
SDA)
-
1
-
-
(1)
(1)
120
-
-
-
500
-
-
-
-
-
-
5
80⁽⁷⁾
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ms
ns
1. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be less than 120 ns when f_C < 1 MHz.
2. Characterized only, not tested in production.
3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
4. t_CLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 V_CC or
0.7 V_CC, assuming that the Rbus × Cbus time constant is within the values specified in Figure 13.
5. WC=0 set up time condition to enable the execution of a WRITE command.
6. WC=0 hold time condition to enable the execution of a WRITE command.
7. 50100 ns for devices identified by process letter A.
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Doc ID 16459 Rev 26